View L9D345G72BG5_4816158.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated module products logic devices incorporated www.logicdevices.com 1 jul 06, 2009 lds-L9D345G72BG5-a 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product ddr3 integrated module [imod]: ? vcc=vccq=1.5v 0.075v ? 1.5v center-terminated, push/pull i/o ? package: 25mm x 25mm, 16 x 16 matrix w/ 255 balls ? matrix ball pitch: 1.00mm space saving footprint thermally enhanced, impedance matched, integrated packaging differential, bidirectional data strobe 8n-bit prefetch architecture 8 internal banks (per word, 9 bytes integrated in package) nominal and dynamic on-die termina- tion (odt) for data, strobe, and mask signals. cas (read) latency (cl): 6, 8, and 10 cas (write) latency (cwl): 6, 7 and 8 fixed burst length (bl) of 8 and burst chop (bc) of 4 selectable bc4 or bl8 on-the- y (otf) features self/auto refresh modes operating temperature range (case temp=tc) ? industrial: -40 ? c to 85 ? c supporting self & auto refresh ? extended: -40 ? c to 105 ? c; manual refresh only ? mil-temp: -55 ? c to 125 ? c; manual refresh only core clocking frequencies: ? industrial: 667mhz, 533mhz and 400mhz ? extended: 533mhz and 400mhz ? mil-temp: 400mhz data transfer rates: ? industrial: 1333, 1066 and 800 mbps ? extended: 1066 and 800 mbps ? mil-temp: 800 mbps write leveling multipurpose register output driver calibration 20% space savings while provid- ing a surface mount friendly pitch (1.00mm) reduced i/o (46%) 25% improvement in routings for your memory array reduced trace lengths due to the highly integrated, impedance matched packaging thermally enhanced packaging technology allow silicon integration without performance degradation due to power dissipation (heat) high tce organic laminate inter- poser for improved glass stability over a wide operating temperature suitability of use in high reliability applications requiring mil-temp, non- hermetic device operation bene ts *note: this integrated product is currently under consideration. latest product status, information, and/ or corresponding documents should be obtained from ldi prior to your design considerations. o rder n umber s peed g rade d evice g rade p kg f ootprint i/o p itch p kg n o . 25mm x 25mm 255 ddr3-1333 ddr3-1066 ddr3-800 industrial extended mil-temp L9D345G72BG5i15 L9D345G72BG5e19 L9D345G72BG5m25 imod part information bg5 1.00mm
area 625 mm 2 ~20% i/o 255 balls/locaons 46% monolithic soluon imod soluon 5 x 96 pins = 480 pins total s a v i n g s o p t i o n s 5 x 139.5mm + component space = ~775mm 22 25.0 25.0 ddr3 9.0mm x 15.5mm 96 ball fbga industrial extended mil-temp ddr3-1333 ddr3-1066 ddr3-800 15 19 25 L9D345G72BG5i15 L9D345G72BG5e19 L9D345G72BG5m25 667/533/400 533/400 400 1333/1066/800 1066/800 800 10-10-10/8-8-8/6-6-6 8-8-8/6-6-6 6-6-6 15 15 15 15 15 15 15 15 15 device grade core freq. [mhz] support data rate [mbps] support target t rcd- t rp-cl speed grade speed mark part ordering information t rcd [ns] t rp [ns] cl [ns] ddr3 9.0mm x 15.5mm 96 ball fbga ddr3 9.0mm x 15.5mm 96 ball fbga ddr3 9.0mm x 15.5mm 96 ball fbga ddr3 9.0mm x 15.5mm 96 ball fbga logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 2 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product i ntegrated vs . m onolithic s olutions - highlights t able 1: k ey t iming p arameters
sample part number: l 9d345g72bg5m15 total density= 4.5gb speed grade t ck = 2.50ns t ck = 1.875ns t ck = 1.5ns 25 19 15 45g l9d3 temperature industrial temperature extended temperature military temperature i e m note: not all options can be combined. please see our part catalog for available offerings. 72 bg5 ddr3 imod organization= 64m x 72 25 x 25mm pbga code code logic devices incorporated www.logicdevices.com 3 jul 06, 2009 lds-L9D345G72BG5-a 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product features f igure 1 - 1gb ddr3 p art n umbers con guration refresh count row addressing back addressing column addressing [8 meg x 8 banks x 16] x 4.5 8k 8k (a[12:0]) 8 (ba[2:0]) 1k (a[9:0]) parameter 64 meg x 72 t able 2: a ddressing
bank active reading writing activating refreshing self refresh idle active power- down zq calibration from any state power applied reset procedure power on initialization mrs, mpr, write leveling preharge power- down writing automatic sequence command sequence preharging read read read read ap read ap read ap pre, prea pre, prea pre, prea write write cke l cke l cke l write write ap write ap write ap pde pde pdx pdx srx sre ref mrs act reset zqcl zqcl/zqcs reading act = activate prea=precharge all srx = self refresh exit mpr = multipurpose register read = rd, rds4, rds8 write = wr, wrs4, wrs8 mrs = mode register set read ap = rdap, rdaps4, rdaps8 write ap = wrap, wraps4, wraps8 pde = power-down entry ref = refresh zqcl = zq long calibration pdx = power-down exit reset = start reset procedure zqcs = zq short calibration pre = precharge sre = self refresh entry logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 4 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product state diagram f igure 2 - s implified s tate d iagram
logic devices incorporated www.logicdevices.com 5 jul 06, 2009 lds-L9D345G72BG5-a 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product the ddr3 sdram uses double data rate architecture to achieve high speed operation. the double data rate (ddr) architecture is an 8n prefetch with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr3 sdram consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal memory core and eight corresponding n-bit-wide, one-half-clock-cycle data transfer at the i/o pin. the differential strobes (ldqsx, ldqsx\, udqsx, udqsx\) is transmitted externally, along with data, for use in data capture at the ddr3 sdram input receiver. dqs is center-aligned with data for writes. the read data is transmitted by the ddr3 sdram and edge-aligned to the data strobes. the ddr3 sdram operates from a differential clock (ckx, ckx\). the crossing of ck going high and ck\ going low is referred to as the posi- tive edge of clock (ck). control, command, and address signals are reg- istered at every positive edge of ck. input data is registered on the rst rising edge of dqs after the write preamble, and output data is refer- enced on the rst rising edge of dqs after the read preamble. read and write accesses to the ddr3 sdram are burst-oriented. accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an activate command, which is then followed by a read or write command. the address bits registered coincident with the acti- vate command are used to select the bank and the starting column loca- tion for the burst access. ddr3 sdram devices use read and write bl8 and bc4. an auto precharge function may be enabled to provide a self-timed row pre- charge that is initiated at the end of the burst access. as with standard ddr sdram devices, the pipelined, multi-bank architec- ture of the ddr3 sdram allows for concurrent operation, thereby provid- ing high bandwidth by hiding row precharge and activation time. a self refresh mode is provided for all temperature grade offerings along with auto self refresh for industrial product, as well as, power- saving, power-down mode. functional description i ndustrial t emperature the industrial temperature (i) device requires the case temperature not exceed -40 ? c or +85 ? c. jedec speci cations require the refresh rate to double when tc exceeds +85 ? c; this also requires use of the high- temperature self refresh option. additionally, odt resistance and the input/output impedance must be derated when the tc is <0 ? c or >+85 ? c. e xtended t emperature the extended temperature (e) device requires the case temperature not exceed -40 ? c or +105 ? c. jedec speci cations require the refresh rate to double when tc exceeds +85 ? c; this also requires use of the high- temperature self refresh option. additionally, odt resistance and the input/output impedance must be derated when the tc is <0 ? c or >85 ? c. m ilitary , e xtreme o perating t emperature the mil-temp (m) device requires the case temperature not exceed -55 ? c or +125 ? c. jedec requires the refresh rate double when tc exceeds +85 ? c and ldi recommends an additional derating as speci ed in this document as to properly maintain the dram core cell charge at tempera- tures above tc>105 ? c.
d0 rst\ vss vssq vcc vccq a 0- a 12, ba 0-1 a, ba cs 0 \ ck 0 ck 0 \ ldqs 0 ldqs 0 \ udqs 0 udqs 0 \ cke 0 cas 0 \ ras 0 \ we 0 \ ldm 0 udm 0 dq 0 dq 7 dq 8 dq 15 dq 0 dq 7 dq 8 dq 15 a, ba d1 dq 0 dq 7 dq 8 dq 15 dq 16 dq 23 dq 24 dq 31 a, ba d2 dq 0 dq 7 dq 8 dq 15 dq 32 dq 39 dq 40 dq 47 a, ba d3 dq 0 dq 7 dq 8 dq 15 dq 48 dq 55 dq 56 dq 63 vccq vcc vssq vss reset\ rst\ vss vssq vcc vccq rst\ vss vssq vcc vccq rst\ vss vssq vcc vccq cs 1 \ ck 1 ck 1 \ ldqs 1 ldqs 1 \ udqs 1 udqs 1 \ cke 1 cas 1 \ ras 1 \ we 1 \ ldm 1 udm 1 cs 2 \ ck 2 ck 2 \ ldqs 2 ldqs 2 \ udqs 2 udqs 2 \ cke 2 cas 2 \ ras 2 \ we 2 \ ldm 2 udm 2 cs 3 \ ck 3 ck 3 \ ldqs 3 ldqs 3 \ udqs 3 udqs 3 \ cke 3 cas 3 \ ras 3 \ we 3 \ ldm 3 udm 3 a, ba d4 dq 0 dq 7 dq 8 dq 15 dq 64 dq 71 rst\ vss vssq vcc vccq cs 4 \ ck 4 ck 4 \ ldqs 4 ldqs 4 \ udqs 4 udqs 4 \ cke 4 cas 4 \ ras 4 \ we 4 \ ldm 4 udm 4 nc nc nc nc nc nc nc nc logic devices incorporated www.logicdevices.com 6 jul 06, 2009 lds-L9D345G72BG5-a 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 3 - f unctional b lock d iagram
L9D345G72BG5 advance information a 12345678910111213141516 a dq0 dq14 dq15 vss vss a9 a10 a11 a8 vccq vccq dq16 dq17 dq31 vss a b dq1 dq2 dq12 dq13 vss vss a0 a7 a6 a1 vcc vcc dq18 dq19 dq29 dq30 b c dq3 dq4 dq10 dq11 vcc vcc a2 a5 a4 a3 vss vss dq20 dq21 dq27 dq28 c d dq6 dq5 dq8 dq9 vccq vccq a12 rfu ba2 rfu vss vss dq22 dq23 dq26 dq25 d e dq7 ldm0 vcc udm0 udqs3 ldqs0 udqs0 ba0 ba1 ldqs1 udqs1 vrefda ldm1 vss nc dq24 e f cas0\ we0\ vcc clk0 ldqs3 udqs3\ ldqs0\ udqs0\ dnu udqs1\ ldqs1\ ras1\ we1\ vss udm1 clk1 f g cs0\ ras0\ vcc cke0 clk0\ ldqs3\ vssq vssq vssq vssq reset\ cas1\ cs1\ vss clk1\ cke1 g h vss vss vcc vccq vss zq0 vssq vssq vssq vssq zq1 vcc vss vss vccq vcc h j vss vss vcc vccq vss vrefca vssq vssq vssq vssq zq2 vcc vss vss vccq vcc j k clk3\ cke3 vcc cs3\ ldqs4 udqs4\ vssq vssq vssq vssq dnu clk2\ cke2 vss ras2\ cs2\ k l nc clk3 vcc cas3\ ras3 \ odt ldqs4\ zq3 nc/zq4 ldqs2\ udqs2\ ldqs2 clk2 vss we2\ cas2\ l m dq56 udm3 vcc we3\ ldm3 cke4 nc clk4 cas4\ we4\ ras4\ cs4\ udm2 vss ldm2 dq39 m n dq57 dq58 dq55 dq54 udqs4 clk4\ nc nc dq71 dq70 ldm4 udqs2 dq41 dq40 dq37 dq38 n p dq60 dq59 dq53 dq52 vss vss nc nc dq69 dq68 vcc vcc dq43 dq42 dq36 dq35 p r dq62 dq61 dq51 dq50 vcc vcc nc nc dq67 dq66 vss vss dq45 dq44 dq34 dq33 r t vss dq63 dq49 dq48 vccq vccq nc nc dq65 dq64 vss vss dq47 dq46 dq32 vcc t 12345678910111213141516 gnd (core) v+ (core powe r) unpopulate d address gnd (i/o) v+ (i/o power) nc dnu data io cntrl level ref logic devices incorporated www.logicdevices.com 7 jul 06, 2009 lds-L9D345G72BG5-a 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 4 - sdram - ddr3 p inout t op v iew ball /signal location (pbga)
logic devices incorporated www.logicdevices.com 8 jul 06, 2009 lds-L9D345G72BG5-a 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 3 - b all /s ignal l ocation and d escription ball assignments symbol type description b7, b10, c7, c10, c9, c8, b9, b8, a10, a7, a8, a9, d7 e8, e9, d9 d10, d8 f4, g5, f16, g15, l13, k12, l2, k1, m8, n6 g4, g16, k13, k2, m6 g1, g13, k16, k4, m12 e2, e4, e13, f15, m15, m13, m5, m2, n11 g2, f12, k15, l5, m11 f1, g12, l16, l4, m9 f2, f13, l15, m4, m10 a 0, a 1, a 2, a 3, a 4, a 5, a 6, a 7, a 8, a 9, a 10 /ap, a 11, a 12 /bc ba 0 , ba 1, ba 2 rfu clk 0 , clk 0 \, clk 1 , clk 1 \, clk 2 , clk 2 \, clk 3 , clk 3 \, clk 4 , clk 4 \ cke 0, cke 1 , cke 2 , cke 3 , cke 4 cs 0 \, cs 1 \, cs 2 \, cs 3 \, cs 4 \ ldmx, udmx, ldmx, udmx, ldmx, udmx, ldmx, udmx ldmx ras0\, ras1\, ras2\, ras3\, ras4\ cas0\, cas1\, cas2\, cas3\, cas4\ we 0 \, we 1 \, we 2 \, we 3 \, we 4 \ input input input input input input input input input input address inputs: provide the row address for activate commands, and the column address and auto precharge bit (a10) for ready/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge com- mand determines whether the precharge applies to one bank (a10 low), bank selected by ba[2:0] or all banks (a10 high). the address inputs also provide the op-code during a load mode command. address inputs are referenced to vrefca. a12/bc#: when enabled in the mode register (mr), a12 is sampled during read and write commands to determine whether burst chop, low = bc4 burst chop). bank address inputs: ba[2:0] de ne the bank to which an activate, read, write, or precharge command is being applied. ba[2:0] de ne which mode register (mr0, mr1, mre, or mr3) is loaded during the load mode command. ba[2:0] are referenced to vrefca. future address: a13, a14 clock: ckx and ckx\ are differential clock inputs, one differential pair per word, ve words contained in the l9d3xxg72 product. all control and address input signals are sam- pled on the crossing of the positive edge of ckx and the negative edge of ckx\. output data strobes (udqsx/udqsx\ and ldqsx/ldqsx\) is referenced to the crossing of ckx and ckx\. clock enable: cke enables and disables internal circuitry and clocks on the sdram. the speci c circuitry that is enabled/disabled is dependent upon the ddr3 sdram con gura- tion and operating mode. taking cke low provides precharge power-down and self refresh operations (all banks idle), or active power-down (row active in any bank). cke is synchronous for power-down entry and exit and for self refresh entry. cke is asynchronous for self refresh exit. input buffers (excluding ckx, ckx\, cke, reset#, and odt) are disabled during self refresh. cke is referenced to vrefca. chip select: cs\ enables (registered low) and disables the command decoder. all com- mands are masked when cs\ is registered high. cs\ provides for external rank selection on systems with multiple ranks. cs\ is considered part of the command code. cs\ is referenced to vrefca. input data mask: ldmx is the lower-byte of a word, udmx is the upperbyte of a word, the l9d3xxg72 contains ve words. the data mask input, masks write data. lower byte data masked when ldmx is sampled high, upper byte data masked when udmx is sampled high. the udmx and ldmx pins are structured as inputs only, the pins electrical loading is designed to match that of the dq and ldqsx, ldqsx\, udqsx, and udqsx\ pins. row address strobe/select: de nes the command being entered along cas\, we\, and cs\. this input pin is referenced to vrefca. column address strobe/select: de nes the command being entered along with ras\, we\, and cs\. this input pin is referenced to vrefca. write enable input: de nes the command being entered along with cas\, ras\,, and cs\. this input pin is referenced to vrefca.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 9 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 3 - b all /s ignal l ocation and d escription c ontinued ball assignments symbol type description l6 g11 e6, e10, l12, f5, k5, f7, f11, l10, g6, l7 e7, e11, n12, e5, n5, f8, f10, l11, f6, k6 a2, b1, b2, c1, c2, d2, d1, e1 d3, d4, c3, c4, b3, b4, a3, a4 a13, a14, b13, b14, c13, c14, d13, d14 e16, d16, d15, c15, c16, b15, b16, a15 t15, r16, r15, p16, p15, n15, n16, m16 n14, n13, p14, p13, r14, r13, t14, t13 t4, t3, r4, r3, p4, p3, n4, n3 odt reset\ ldqsx, ldqsx\ udqsx, udqsx\ dq 0, dq 1, dq 2, dq 3, dq 4, dq 5, dq 6, dq 7 dq 8, dq 9, dq 10, dq 11, dq 12, dq 13, dq 14, dq 15 dq 16, dq 17, dq 18, dq 19, dq 20, dq 21, dq 22, dq 23 dq 24, dq 25, dq 26, dq 27, dq 28, dq 29, dq 30, dq 31 dq 32, dq 33, dq 34, dq 35, dq 36, dq 37, dq 38, dq 39 dq 40, dq 41, dq 42, dq 43, dq 44, dq 45, dq 46, dq 47 dq 48, dq 49, dq 50, dq 51, dq 52, dq 53, dq 54, dq 55 input input input input i/o i/o i/o i/o i/o i/o i/o on-die termination: odt enables (when registered high) and disables termination resis- tance internal to the ddr3 sdram. when enabled in normal operation, odt is only applied to each of the following signals: dq[63:0], ldqsx, ldqsx\, udqsx, udqsx\, udmx and ldmx. the odt input is ignored if disabled via the load mode register command. odt is referenced to vrefca. reset: an input control pin, active low referenced to vss. the reset\ input receiver is a cmos input de ned as a rail to rail signal with dc high 0.8 x vcc and dc low 0.2 x vccq. reset\ assertion and de-assertion are asynchronous. data strobe, low byte (per word): output, edge-aligned with read data. input, center- aligned with write data. data strobe, high byte (per word): output, edge-aligned with read data. input, center- aligned with write data. data input/output: low byte, low word (word 1). pin referenced to vrefdq. data input/output: high byte, low word (word 1). pin referenced to vrefdq. data input/output: low byte, word 2. pin referenced to vrefdq. data input/output: high byte, word 2. pin referenced to vrefdq. data input/output: low byte, word 3. pin referenced to vrefdq. data input/output: high byte, word 3. pin referenced to vrefdq. data input/output: low byte, high word (word 4). pin referenced to vrefdq.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 10 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 3 - b all /s ignal l ocation and d escription c ontinued ball assignments symbol type description m1, n1, n2, p2, p1, r2, r1, t2 t10, t9, r10, r9, p10, p9, n10, n9 b11, b12, c5, c6, e3, f3, g3, h3, h12, h16, j3, j12, j16, k3, l3, m3, p11, p12, r5, r6, t16 a11, a12, d5, d6, h4, h15, j4, j15, t5, t6 a5, a6, a16, b5, b6, c11, c12, d11, d12, e14, f14, g14, h1, h2, h5, h13, h14, j1, j2, j5, j13, j14, k14, l14, m14, p5, p6, r11, r12, t1, t11, t12 g7, g8, g9, g10, h7, h8, h9, h10, j7, j8, j9, j10, k7, k8, k9, k10 j6 e12 h6, h11, j11, l8, l9 a1 e15, l1 dq 56, dq 57, dq 58, dq 59, dq 60, dq 61, dq 62, dq 63 dq 64, dq 65, dq 66, dq 67, dq 68, dq 69, dq 70, dq 71 v cc v cc q v ss v ss q v refca v refdq zqx unpopulated nc i/o i/o supply supply supply supply supply supply ref - data input/output: high byte, high word (word 4). pin referenced to vrefdq. data input/output: high byte, high word (word 5). pin referenced to vrefdq. power supply: 1.5v 0.075v data i/o supply: 1.5v 0.075v ground data i/o ground: isolated from core for improved noise immunity voltage reference core: vrefca must be maintained at all times voltage reference i/o: vrefdq must be maintained at all times. external reference for output drive calibration unpopulated, un-plated matrix location(s) no connect: these ball locations have no electrical connection internally. locations other than those indicating an upgrade or alternative function should be left isolated (non-connected)
24.90 25.10 24.90 25.10 19.05 nom 1.27 nom 1.27 nom 1.27 nom 255 x 0.762 nom 0.50 max 2.00 max 0.61 nom 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t note: all dimensions in mm logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 11 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 5 - m echanical d rawing
p ackage o utline d imensions logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 12 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product notes: 1. v cc and v cc q must be within 300mv of each other at all times and v ref must not be greater than 0.6 x v cc q. when v cc and v cc q are less than 500mv, v ref may be 300mv. 2. max operating case temperature. t c is measured in the center of the package. 3. device functionality is not guaranteed if the dram device exceeds the maximum t c during operation. notes: 1. v cc = +1.5v 0.075mv, v ccq = v cc , v ref = v ss , f= 100mhz, t c = 25 c, v out (dc ) = 0.5 x v ccq , v out (peak to peak) = 0.1v 2. dm input is grouped with i/o pins, re ecting the signal is grouped with dq and therefore matched in loading. 3. c ccqs is for dqs vs. dqs\ 4. c dio = cio (dq) - 0.5 x (cio [dqs] + cio [dqs\]) 5. excludes ck, ck\ 6. c di_cntl = ci(cntl) - 0.5 x (cck[ck] + cck [ck\]); cntl = odt, cs\ and cke 7. c di_cmd_addr = ci (cmd_addr) - 0.5 x (cck [ck] + cck [ck\]); cmd = ras\, cas\, and we\ addr = [n:0] capacitance parameter symbol min max min max min max units notes ck and ck\ ? c: ck to ck\ single-end i/o: dq, dm differential i/o: dqs, dqs\ ? c: dqs to dqs\ ? c: dq to dqs ? c: cntl to ck ? c: cmd_addr to ck inputs (ras\, cas\, we\, cs\, cke, addr) t able 6: i nput /o utput c apacitance c ck c dck c 10 c 10 c ccqs c di0 c di_cntl c di_cmd_addr c i_shared 3.1 0 1.5 1.5 0 -0.5 -0.5 -0.5 2.9 6.2 0.2 3.0 3.0 0.2 0.3 0.3 0.3 5.5 6.2 0.2 3.0 3.0 0.2 0.3 0.3 0.3 5.3 3.0 0 1.5 1.5 0 -0.5 -0.5 -0.5 2.9 6.1 0.2 2.5 2.5 0.2 0.3 0.3 0.3 5.1 pf pf pf pf pf pf pf pf pf 2 3 3 4 6 7 5 ddr3-800 ddr3-1066 ddr3-1333 3.1 0 1.5 1.5 0 -0.5 -0.5 -0.5 2.9 symbol parameter min max units notes v cc v cc q v in , v out t c industrial t c extended t c miltemp t stg v v v c c c c 1 1 1 2,3 2,3 2,3 2,3 t able 5: a bsolute m aximum r atings 1.975 1.975 1.975 85 105 125 120 -0.4 -0.4 -0.4 0 -40 -55 -55 v cc supply voltage relative to v ss v cc supply voltage relative to v ss q voltage on any pin relative to v ss operating case temperature operating case temperature operating case temperature storage temperature
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 13 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product i cc parameter 6-6-6 8-8-8 10-10-10 units t ck (min) i cc cl i cc t rcd (min) i cc trc (min) i cc t ras (min) i cc t rp (min) i cc t faw t rrd i cc t rfc t able 8: t iming p arameters for i cc m easurements - c lock u nits ns ck ck ck ck ck ck ck ck 1.5 10 10 34 24 10 30 5 74 1.875 8 8 28 20 8 27 6 59 ddr3-800 -25 ddr3-1066 -19 ddr3-1333 -15 x72 x72 64m x 16 (4.5x) 2.5 6 6 21 15 6 20 4 44
ck, ck\ cke sub-loop cs\ ras\ cas\ we\ odt ba [2:0] a [15:11] a [10] a [9:7] a [6:3] a [2:0] 00110000000 10000000000 10000000000 11110000000 11110000000 00100000000 001100000f0 100000000f0 100000000f0 111100000f0 111100000f0 001000000f0 1 2 3 4 5 6 7 repeat sub-loop 0, use ba [2:0] = 6 repeat sub-loop 0, use ba [2:0] = 7 - - - - - - - - repeat cycles n rc +1 through n rc +4 until 2 x rc - 1, truncate if needed repeat sub-loop 0, use ba [2:0] = 1 repeat sub-loop 0, use ba [2:0] = 2 repeat sub-loop 0, use ba [2:0] = 3 repeat sub-loop 0, use ba [2:0] = 4 repeat sub-loop 0, use ba [2:0] = 5 d\ d\ pre repeat cycles 1 through 4 until n ras - 1, truncate if needed repeat cycles 1 through 4 until n rc - 1, truncate if needed repeat cycles n rc +1 through n rc +4 until n rc - 1 + n ras - 1, truncate if needed - - - - d\ d\ pre act d d 4 x n rc 6 x n rc 8 x n rc 10 x n rc 12 x n rc 14 x n rc n rc + 3 n rc + 4 - n rc + n ras - 2 x nrc - n ras - n rc n rc + 1 n rc + 2 cycle number command 0 data 1 2 act d d 3 4 0 static high toggling logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 14 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 9: i cc 0 m easurement l oop
ck, ck\ cke sub-loop cs\ ras\ cas\ we\ odt ba [2:0] a [15:11] a [10] a [9:7] a [6:3] a [2:0] 00110000000 10000000000 10000000000 11110000000 11110000000 01010000000 00100000000 001100000f0 100000000f0 100000000f0 111100000f0 111100000f0 010100000f0 001000000f0 1 2 3 4 5 6 7 cycle number command data 0 1 2 act d d - 3 4 - nrcd - nras - nrc n rc +1 nrc +2 n rc +3 n rc +4 - n rc + nrcd - n rc + nras 2 x n rc 2 x n rc 2 x n rc 2 x n rc 2 x n rc 2 x n rc 2 x n rc d\ d\ rd pre act d d d\ d\ rd pre repeat sub-loop 0, use ba [2:0] = 1 - 00110011 - repeat sub-loop 0, use ba [2:0] = 2 repeat sub-loop 0, use ba [2:0] = 3 repeat sub-loop 0, use ba [2:0] = 4 repeat sub-loop 0, use ba [2:0] = 5 repeat sub-loop 0, use ba [2:0] = 6 repeat sub-loop 0, use ba [2:0] = 7 repeat cycles 1 through 4 until nrcd - 1, truncate if needed repeat cycles 1 through 4 until nras - 1, truncate if needed repeat cycles 1 through 4 until nrc - 1, truncate if needed repeat cycles nrc + 1 through nrc + 4 until nrc + nrcd - 1, truncate if needed repeat cycles nrc + 1 through nrc + 4 until nrc + nras - 1, truncate if needed - - - - - - - - 00000000 - toggling static high 0 repeat cycle nrc + 1 through nrc + 4 until 2 x nrc - 1, truncate if needed logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 15 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 10: i cc 1 m easurement l oop
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 16 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 11: i cc m easurement c onditions f or p ower -d own c urrents name timing pattern cke external clock t ck t rc t ras t rcd t rrd t rc cl al cs\ command inputs row/column addr bank address dm data i/o output buffer dq, dqs odt burst length active bank(s) idle bank(s) special notes n/a low toggling t ck (min) i cc n\a n\a n\a n\a n\a n\a n\a high low low low low mid-level enabled enabled, off 8 none all n\a n/a low toggling t ck (min) i cc n\a n\a n\a n\a n\a n\a n\a high low low low low mid-level enabled enabled, off 8 none all n\a n/a high toggling t ck (min) i cc n\a n\a n\a n\a n\a n\a n\a high low low low low mid-level enabled enabled, off 8 none all n\a n/a low toggling t ck (min) i cc n\a n\a n\a n\a n\a n\a n\a high low low low low mid-level enabled enabled, off 8 none all n\a icc2p0 precharge power- down current (slow exit) icc2p1 precharge power- down current (fast exit) icc2q precharge quiet standby current icc3p active power- down current
ck, ck\ cke sub-loop cs\ ras\ cas\ we\ odt ba [2:0] a [15:11] a [10] a [9:7] a [6:3] a [2:0] 10000000000 10000000000 111100000f0 111100000f0 1 2 3 4 5 6 7 cycle number command data 0 1 0d d 2d\ 3d\ repeat sub-loop 0, use ba [2:0] = 7 - - - - 4-7 8-11 repeat sub-loop 0, use ba [2:0] = 1 repeat sub-loop 0, use ba [2:0] = 2 repeat sub-loop 0, use ba [2:0] = 3 repeat sub-loop 0, use ba [2:0] = 4 repeat sub-loop 0, use ba [2:0] = 5 repeat sub-loop 0, use ba [2:0] = 6 static high toggling 12-15 16-19 20-23 24-27 28-31 logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 17 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 12: i cc 2 n / i cc 3 n m easurement l oop
ck, ck\ cke sub-loop cs\ ras\ cas\ we\ odt ba [2:0] a [15:11] a [10] a [9:7] a [6:3] a [2:0] 10000000000 10000000000 111100000f0 111100000f0 1 2 3 4 5 6 7 cycle number command data toggling static high 0 0 3 12-15 28-31 d - 1d - 2d\ - d\ - 4-7 repeat sub-loop 0, use ba [2:0] = 1; odt = 0 8-11 repeat sub-loop 0, use ba [2:0] = 2; odt = 1 repeat sub-loop 0, use ba [2:0] = 3; odt = 1 16-19 repeat sub-loop 0, use ba [2:0] = 4; odt = 0 20-23 repeat sub-loop 0, use ba [2:0] = 5; odt = 0 24-27 repeat sub-loop 0, use ba [2:0] = 6; odt = 1 repeat sub-loop 0, use ba [2:0] = 7; odt = 1 logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 18 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 13: i cc 2 nt m easurement l oop
ck, ck\ cke sub-loop cs\ ras\ cas\ we\ odt ba [2:0] a [15:11] a [10] a [9:7] a [6:3] a [2:0] 01010000000 10000000000 11110000000 11110000000 010100000f0 100000000f0 111100000f0 111100000f0 1 2 3 4 5 6 7 data 0 static high toggling 56-63 0 1 2 5 8-15 cycle number command rd d d\ d\ rd 3 4 - d d\ d\ 6 7 32-39 16-23 24-31 40-47 48-55 00000000 - - - 00110011 repeat sub-loop 0, use ba [2:0] = 7 - - repeat sub-loop 0, use ba [2:0] = 1 repeat sub-loop 0, use ba [2:0] = 2 repeat sub-loop 0, use ba [2:0] = 3 repeat sub-loop 0, use ba [2:0] = 4 repeat sub-loop 0, use ba [2:0] = 5 repeat sub-loop 0, use ba [2:0] = 6 logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 19 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 14: i cc 4 r m easurement l oop
ck, ck\ cke sub-loop cs\ ras\ cas\ we\ odt ba [2:0] a [15:11] a [10] a [9:7] a [6:3] a [2:0] 01001000000 10001000000 11111000000 11111000000 010010000f0 100010000f0 111110000f0 111110000f0 1 2 3 4 5 6 7 data 1d - wr toggling stac high 0 0 3 6 2d\ - 00000000 cycle number command d\ - 4wr 00110011 5d - d\ - 7d\ - 8-15 repeat sub-loop 0, use ba [2:0] = 1 16-23 repeat sub-loop 0, use ba [2:0] = 2 24-31 repeat sub-loop 0, use ba [2:0] = 3 32-39 repeat sub-loop 0, use ba [2:0] = 4 40-47 repeat sub-loop 0, use ba [2:0] = 5 48-55 repeat sub-loop 0, use ba [2:0] = 6 56-63 repeat sub-loop 0, use ba [2:0] = 7 logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 20 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 15: i cc 4 w m easurement l oop
ck, ck\ cke sub-loop cs\ ras\ cas\ we\ odt ba [2:0] a [15:11] a [10] a [9:7] a [6:3] a [2:0] 0 1b 1c 1d 1e 1f 1g 1h 2 9-12 13-16 cycle number command data 1 0 17-20 21-24 25-28 29-32 33-n rfc-1 repeat sub-loop 1a, use ba [2:0] = 1 repeat sub-loop 1a, use ba [2:0] = 2 1a 2 3 4 5-8 static high toggling ref d d d\ d\ repeat sub-loop 1a, use ba [2:0] = 4 repeat sub-loop 1a, use ba [2:0] = 5 repeat sub-loop 1a, use ba [2:0] = 6 repeat sub-loop 1a, use ba [2:0] = 3 repeat sub-loop 1a, use ba [2:0] = 7 repeat sub-loop 1a through 1h until n rfc - 1, truncate if needed logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 21 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 16: i cc 5 b m easurement l oop
p ackage o utline d imensions logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 22 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 17: i cc m easurement l oop i cc test icc8: reset icc6e/m: self refresh current icc6: self refresh current extended or mil temperature range, tc = -40c to 85c or -55c to 125c industrial range tc =-40c to 85c cke external clock t ck t rc t ras t rcd t rrd t rc cl al cs\ command inputs row/colmun addresses bank addresses data i/o output buffer dq, dqs odt burst length active banks idle banks srt asr low off, ck and ck\ = low n\a n\a n\a n\a n\a n\a n\a n\a mid-level mid-level mid-level mid-level mid-level enabled enabled, mid-level n\a n\a n\a disabled (normal) disabled low off, ck and ck\ = low n\a n\a n\a n\a n\a n\a n\a n\a mid-level mid-level mid-level mid-level mid-level enabled enabled, mid-level n\a n\a n\a enabled (extended) disabled mid-level mid-level n\a n\a n\a n\a n\a n\a n\a n\a mid-level mid-level mid-level mid-level mid-level mid-level mid-level n\a none all n\a n\a
ck, ck\ cke sub-loop cs\ ras\ cas\ we\ odt ba [2:0] a [15:11] a [10] a [9:7] a [6:3] a [2:0] 00110000000 01010001000 10000000000 001101000f0 010101010f0 100001000f0 2 3 100003000f0 5 6 7 8 100007000f0 001100000f0 010100010f0 100000000f0 00110100000 01010101000 10000100000 12 13 10000300000 15 16 17 18 10000700000 cycle number command data 1 0 2 - 00000000 - 3 n rrd n rrd + 1 n rrd + 2 n rrd + 3 2 x n rrd 3x n rrd 4 x n rrd 4 x n rrd + 1 n faw n faw + n rrd n faw + 2x n rrd n faw + 3x n rrd n faw + 4x n rrd n faw + 4x n rrd+1 2 x n faw 2 x n faw + 1 2 x n faw + 2 3 x nfaw + nrrd 3 x nfaw + 2x nrrd 2 x n faw + 3 2 x n faw + n rrd 2 x n faw + n rrd+1 2 x n faw + n rrd+2 2 x n faw + n rrd+3 2 x nfaw + 2x n rrd 1 4 9 10 11 14 static high toggling act rda d act 3 x nfaw + 3x nrrd 3 x nfaw + 4x nrrd 3 x nfaw + 4x nrrd +1 0 d act rda - repeat cycle 2 x n faw + 2 until 2 x n faw + n rrd - 1 19 2 x n faw + 3x n rrd 2 x n faw + 4x n rrd 2 x n faw+4x n rrd+1 3 x nfaw repeat sub-loop 11, use ba[2:0] = 3 - - - repeat sub-loop 1, use ba[2:0] = 5 repeat sub-loop 0, use ba[2:0] = 6 repeat sub-loop 1, use ba[2:0] = 7 repeat cycle n faw + 4 x n rrd until 2 x n faw - 1, if needed rda d - d repeat cycle 2 until n rrd - 1 repeat cycle n rrd + 2 until 2 x n rrd - 1 repeat sub-loop 0, use ba[2:0] = 2 repeat sub-loop 0, use ba[2:0] = 3 repeat cycle 4 x n rrd until n faw - 1, if needed 00110011 repeat sub-loop 10, use ba[2:0] = 2 - - rda d - 00110011 repeat sub-loop 0, use ba[2:0] = 4 d act d repeat cycle 2 x n faw + n rrd + 2 until 2 x n faw + 2 x n rrd - 1 00000000 - repeat cycle 3 x n faw + 4 x n rrd until 4 x n faw - 1, if needed repeat cycle 2 x n faw + 4 x n rrd until 3 x n faw - 1, if needed repeat sub-loop 10, use ba[2:0] = 4 repeat sub-loop 11, use ba[2:0] = 5 repeat sub-loop 10, use ba[2:0] = 6 repeat sub-loop 11, use ba[2:0] = 7 d logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 23 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 18: i cc 7 m easurement l oop
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 24 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product notes: tc = 0 1. c to 85 c; srt and asr are disabled, enabling asr could increase i cc x by up to an additional 2ma. tc = -40 2. c to 105 c; srt and asr are disabled, enabling asr could increase i cc x by up to an additional 2ma. tc = -55 3. c to 125 c; srt and asr are disabled, enabling asr could increase i cc x by up to an additional 2ma. i cc ddr3-800 ddr3-1066 ddr3-1333 units notes icc0 icc1 icc2p0 icc2p1 icc2q icc2n icc2nt icc3p icc3n icc4r icc4w icc5b icc6 icc7 icc8 speed bin 437 456 475 544 578 603 59 76 220 148 191 220 230 299 343 244 316 362 393 506 581 148 154 163 245 250 269 1128 1150 1175 1176 1200 1125 980 1000 1020 30 54 95 1700 1844 1988 i cc 2p + 2ma i cc 2p + 2.1ma i cc 2p + 2.4ma 488 508 637 663 59 76 171 223 265 344 268 349 465 605 173 181 268 273 1275 1300 1421 1450 1077 1100 30 54 1860 2000 i cc 2p + 2ma i cc 2p + 2.1ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ind ext mil-temp ind ext mil-temp ind ext mil-temp ind ext mil-temp ind ext mil-temp ind ext mil-temp ind ext mil-temp ind ext mil-temp ind ext mil-temp ind ext mil-temp ind ext mil-temp ind ext mil-temp ind ext mil-temp ind ext mil-temp ind ext mil-temp 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 t able 19: i cc m aximum l imits 544 731 59 196 300 318 515 196 294 1421 1740 1176 30 2055 i cc 2p + 2ma
p ackage o utline d imensions p ackage o utline d imensions logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 25 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product notes: vcc and vccq must track one another, vccq must be less than or equal 1. to vcc, vss = vssq. vcc and vccq may include ac noise of 50mv (250 khz to 20mhz) in 2. addition to the dc (0hz to 250khz) speci cations, vcc and vccq must be at the same level for valid ac timing parameters. v 3. ref (see table 22). the minimum limit requirement is for testing purposes. the leakage 4. current on the v ref pin should be minimal. notes: v 1. refca (dc) is expected to be approximately 0.5 x vcc and to track vari- ations in the dc level. externally generated peak noise (noncommon mode) on v refca may not exceed 1% x vcc around the v refca (dc) value. peak-to-peak ac noise on v refca should not exceed 2% of v refca (dc). dc values are determined to be less than 20mhz in frequency. dram 2. must meet speci cations if the dram induces additional ac noise greater than 20mhz in frequency. v 3. refdq (dc) is expected to be approximately 0.5 x vcc and to track variations in the dc level. externally generated peak noise (noncom- mon mode) on vrefdq may not exceed 1% x vcc around the vrefdq(dc) value. peak-to-peak ac noise on vrefdq should not exceed 2% of vrefdq(dc). v 4. refdq (dc) may transition to v refdq (sr) and back to v refdq (dc) when in self zrefresh, within restrictions outlined in the self refresh section. v 5. tt is not applied directly to the device. v tt is a system supply for signal termination resistors. min and max values are system-depen- dent. parameter/condition symbol min typ ma x units notes supply voltage i/o supply voltage input leakage current: any input 0v v in v cc , v ref pin 0v v in 1.1v all other pins not under test = 0v vref supply leakage current: v refdq = vcc/2 or v refca = vcc/2 all other pins not under test = 0v v v a a 1,2 1,2 3,4 t able 20: dc e lectrical c haracteristics and o perating c onditions 1.575 1.575 2 1 1.5 1.5 - - 1.425 1.425 -2 -1 all voltages are referenced to vss v cc v cc q i i i vref parameter/condition symbol min typ max units notes vin low; dc/commands/address busses vin high; dc/commands/address busses input reference voltage command/address bus i/o reference voltage dq bus i/o reference voltage dq bus in self refresh command/address termination voltage (system level, not direct dram input) v v v v v v 1,2 2,3 4 5 t able 21: dc e lectrical c haracteristics and i nput c onditions see table 20 v cc 0.51 x v cc 0.51 x v cc v cc - n/a n/a 0.5 x v cc 0.5 x v cc 0.5 x v cc 0.5 x v cc q v ss see table 20 0.49 x v cc 0.49 x v cc v ss - all voltages are referenced to vss v il v ih v ref ca(dc) v ref dq(dc) v ref dq(sr) v tt
p ackage o utline d imensions logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 26 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product input high ac voltage: logic 1 input high ac voltage: logic 1 input high dc voltage: logic 1 input high dc voltage: logic 0 input high ac voltage: logic 0 input high ac voltage: logic 0 input high ac voltage: logic 1 input high ac voltage: logic 1 input high dc voltage: logic 1 input high dc voltage: logic 0 input high ac voltage: logic 0 input high ac voltage: logic 0 +175 +150 +100 -100 -150 -175 - +150 +100 -100 -150 - +175 +150 +100 -100 -150 -175 +175 +150 +100 -100 -150 -175 v ih (ac175) min v ih (ac150) min v ih (dc100) min v il (dc100) max v il (ac150) max v il (ac175) max v ih (ac175) min v ih (ac150) min v ih (dc100) min v il (dc100) max v il (ac150) max v il (ac175) max notes: all voltages are referenced to v 1. ref , v ref is v refca for control, com- mand, and address. all slew rates and setup/hold times are speci ed at the dram ball. v ref is v refdq for dq and dm inputs. input setup timing parameters ( 2. t is and t ds) are referenced at v il (ac)/ v ih (ac), not v ref (dc). input hold timing parameters ( 3. t ih and t dh) are referenced at v il (dc)/ v ih (dc), not v ref (ac). single-ended input slew rate = 1v/ns; maximum input voltage swing 4. under test is 900mv (peak-to-peak). parameter/condition symbol ddr3-900 ddr1333 units command and address t able 22: i nput s witching c onditions dq and dm ddr3-1066 mv mv mv mv mv mv mv mv mv mv mv mv
notes: 1. numbers in diagrams reflect nominal values. minimum v il and v ih levels 0.925v 0.850v 0.780v 0.765v 0.750v 0.735v 0.720v 0.650v 0.575v v ih (ac) v ih (dc) v il (dc) v il (ac) v il and v ih levels with ringback 1.90v 1.50v 0.925v 0.850v 0.780v 0.765v 0.750v 0.735v 0.720v 0.650v 0.575v 0.0v -0.40v v dd q + 0.4v narrow pulse width v dd q v ih (ac) v ih (dc) v ref + ac noise v ref + dc error v ref + dc error v ref + ac noise v il (dq) v il (ac) vss vss 0.4v narrow pulse width logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 27 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product operating conditions f igure 6 - i nput s ignal
f igure 7 & 8: o vershoot /u ndershoot s pecifications maximum amplitude overshoot area v cc /v cc q time (ns) volts (v) maximum amplitude undershoot area time (ns) v ss /v ss q volts (v) figure 7: overshoot figure 8: undershoot ac overshoot/undershoot specification logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 28 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product p ackage o utline d imensions p ackage o utline d imensions parameter ddr3-800 ddr3-1066 dd r3-1333 maximum peak amplitude allowed for overshoot area (see figure 16 on page 38) maximum peak amplitude allowed for overshoot area (see figure 17 on page 39) maximum overshoot area above v cc (see figure 16 on page 38) maximum undershoot area below v ss (see figure 17 on page 39) t able 23: c ontrol and a ddress p ins 0.4v 0.4v 0.4vns 0.4vns 0.4v 0.4v 0.67vns 0.67vns 0.4v 0.4v 0.5vns 0.5vns parameter ddr3-800 ddr3-1066 dd r3-1333 maximum peak amplitude allowed for overshoot area (see figure 16 on page 38) maximum peak amplitude allowed for overshoot area (see figure 17 on page 39) maximum overshoot area above v cc/ v cc q (see figure 16 on page 38) maximum undershoot area below v ss/ v ss q (see figure 17 on page 39) t able 24: c lock , d ata , s trobe , and m ask p ins 0.4v 0.4v 0.15vns 0.15vns 0.4v 0.4v 0.25vns 0.25vns 0.4v 0.4v 0.19vns 0.19vns
p ackage o utline d imensions logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 29 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product parameter/condition symbol min max units notes differential input voltage, logic high - slew differential input voltage, logic low - slew differential input voltage, logic high differential input voltage, logic low differential input crossing voltage relative to vcc/2 for dqs, dqs\, ck, ck\ differential input crossing voltage relative to vcc/2 for ck, ck\ single-ended high level for strobes single-ended high level for ck, ck\ single-ended low level for strobes single-ended low level for ck, ck\ mv mv mv mv mv mv mv mv 4 4 5 6 7 7,8 5 6 t able 25: d ifferential i nput o perating c onditions (ck x , ck x \, dqs x , and dqs x \) n/a -200 v cc /v cc q 2x(v ref -v il (ac)) v ref (dc) + 150 v ref (dc) + 175 v cc q v cc v cc q/2-v il (ac) v cc /2 - v il (ac) +200 n/a 2x(v ih (ac)-v ref ) v ss /v ss q v ref (dc) - 150 v ref (dc) - 175 v cc q/2 + v ih( ac) v cc /2 + v ih( ac v ss q v ss v ih diff(ac)slew v il diff(ac)slew v ih diff(ac) v il diff(ac) v ix v ix(175) v she v sel notes: clock is referenced to vccd and vss. data strobe is referenced to 1. vccq and vssq. reference is v 2. refca (dc) for clock and for v refdq (dc) for strobe. differential input slew rate = 2v/ms. 3. de nes slew rate reference points relative to input crossing voltages. 4. max limit is relative to single-ended signals, the overshoot speci ca- 5. tions are applicable. min limit is relative to single-ended signals, the undershoot speci ca- 6. tions are applicable. the typical value of v 7. ix (ac) is expected to be about 0.5 x vcc of the transmitting device and v ix (ac) is expected to track variations in vcc. v ix (ac) indicates the voltage at which differential input signals must cross. the v 8. ix extended range (175mv) is allowed only for the clock and this v ix extended range is only allowed when the following conditions are met: the single-ended input signals are monotonic, have the single- ended swing v sel , v seh of at least vcc/2 250mv, and the differential slew rate of ck, ck\ is greater than 3v/ns.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 30 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product overshoot/undershoot specifications f igure 9 - v ix for d ifferential s ignals v ix x x x x v cc , v cc q v cc , v cc q ck#, dqs# ck#, dqs# v ix v ix v ix ck, dqs ck, dqs v ss , v ss q v ss , v ss q v cc /2, v cc q/2 v cc /2, v cc q/2 f igure 10 - s ingle -e nded r equirements for d ifferential s ignals v ss or v ss q v cc or v cc q v sel (max) v seh (min) v seh v sel v cc /2 or v cc q/2 ck or dqs
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 31 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product overshoot/undershoot specifications f igure 11 - d efinition of d ifferential ac-s wing and t dvac v ihdiff ( ac ) min v ihdiff ( dc ) min 0.0 v ildiff ( dc ) max v ildiff (max) t dvac v ihdiff (min) v ildiff ( ac ) max half cycle t dvac ck - ck# dq s - dqs # p ackage o utline d imensions slew rate (v/ns) 350mv 300mv -4.0 4.0 3.0 2.0 1.9 1.6 1.4 1.2 1.0 <1.0 t able 26: d ifferential i nput o perating c onditions ( t dvac) for ck x , ck x \, dqs x , and dqs x \ 175 170 167 163 162 161 159 155 150 150 75 57 50 38 34 29 22 13 0 0 below v il (ac) t dvac (ps) at [v ihdiff (ac) to v ildiff (ac)]
p ackage o utline d imensions input edge from to calculation setup hold t able 27: s ingle -e nded i nput s lew r ate input slew rate (linear signals) rising falling rising falling measured v ref v ref v il (dc)max v ih (dc)min v ih (ac)min v il (ac)max v ref v ref v ih (ac) min - v ref v ref - v il (ac) max ? tfs v ref - v il (dc) max ? tfh v ih (dc) min - v ref ? trsh logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 32 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product slew rate definitions for single-ended input signals setup ( t is and t ds) nominal slew rate for a rising signal is de ned as the slew-rate between the last crossing of v ref and the rst crossing v ih (ac) min. setup ( t is and t ds) nominal slew rate for a falling signal is de ned as the slew rate between the last crossing of v ref an the rst crossing of v il (ac) max. hold ( t ih and t dh) nominal slew rate for a rising signal is de ned as the slew rate between the last crossing of v il (dc) max and the rst crossing of v ref . hold ( t ih and t dh) nominal slew rate for a falling signal is de ned as the slew rate between the last crossing of v ih (dc) min and the rst crossing of v ref .
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 33 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product slew rate definitions for single-ended input signals f igure 12 - n ominal s lew r ate d efinition for s ingle -e nded i nput s ignals # #
# #

! ! " ! "
p ackage o utline d imensions input edge from to calculation ck and dqs reference t able 28: d ifferential i nput s lew r ate d efinition input slew rate (linear signals) rising falling measured v ref v ref v ih (ac)min v il( ac)max v ih (diff) min - v il (diff) max ? tr(diff) v ih (diff) min - v il (diff) max ? tf(diff) logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 34 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product slew rate definitions for differential input signals input slew rate for differential signals (ckx, ckx\, udqsx , udqsx\, ldqsx and ldqsx\) are de ned and measured as shown in table 28. the nominal slew rate for a rising signal is de ned as the slew rate between v il (diff) max and v ih (diff) min. the nominal slew rate for a falling signal is de ned as the slew rate between v ih (diff) min and v il (diff) max. f igure 13 - n ominal d ifferential i nput s lew r ate d efinition for dqs, dqs# and ck, ck# %
%

!" #" $ "

logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 35 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product odt characteristics r tt pu r tt pd odt chip in termination mode v cc q dq v ss q i out = i pd - i pu i pu i pd i out v out to other circuitry such as rcv, . . . odt?s effective resistance r tt is de ned by mr1[9,6 and 2]. odt is applied to the dqx, udmx, ldmx, udqsx, udqsx\, ldqsx and ldqsx\ balls. the odt target values are listed in table 29. parameter/condition symbol min typ max units n o t e s r tt effective impedance deviation of vm with respect to v cc q/2 % 1, 2, 4 1, 2, 3, 4 t able 29: o n -d ie t ermination dc e lectrical c haracteristics 5 r tt _eff ? vm -5 see table 30 notes: tolerance limits are applicable after a proper zq calibration has been 1. performed at a stable temperature and voltage (vccq=vcc, vssq-vss). refer to ?odt sensitivity? on page 37 if either the temperature or voltage changes after calibration. measurement de nition for r 2. tt : apply v ih (ac) to a pin under test and measure the current i[v ih (ac)], then apply v il (ac) to pin under test and measure current i[v il (ac)]: v il (ac) - v il (ac) i[vih(ac))-i(v il (ac))] measure voltage (vm) at the tested pin with no load: 3. for extended mil-temp devices, the minimum values are derated by 4. 6% when the device is between -40c and 0c (tc). r tt = 2 x vm vccq ? vm = -1 x 100 f igure 14 - odt l evels and i-v c haracteristics
p ackage o utline d imensions logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 36 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product mr1 [ 9 , 6 , 2 ] 0, 1, 0 0, 0, 1 0, 1, 1 1, 0, 1 1, 0, 0 t able 30: rtt e ffective i mpedances 0.2 x vccq 0.5 x vccq 0.8 x vccq 0.2 x vccq 0.5 x vccq 0.8 x vccq v il (ac) to v ih (ac) 0.2 x vccq 0.5 x vccq 0.8 x vccq 0.2 x vccq 0.5 x vccq 0.8 x vccq v il (ac) to v ih (ac) 0.2 x vccq 0.5 x vccq 0.8 x vccq 0.2 x vccq 0.5 x vccq 0.8 x vccq v il (ac) to v ih (ac) 0.2 x vccq 0.5 x vccq 0.8 x vccq 0.2 x vccq 0.5 x vccq 0.8 x vccq v il (ac) to v ih (ac) 0.2 x vccq 0.5 x vccq 0.8 x vccq 0.2 x vccq 0.5 x vccq 0.8 x vccq v il (ac) to v ih (ac) r tt resistor vout min typ max units 120 60 40 30 20 0.6 0.9 0.9 0.9 0.9 0.9 0.9 0.6 0.9 0.9 0.9 0.9 0.9 0.9 0.6 0.9 0.9 0.9 0.9 0.9 0.9 0.6 0.9 0.9 0.9 0.9 0.9 0.9 0.6 0.9 0.9 0.9 0.9 0.9 0.9 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 rzq/1 rzq/1 rzq/1 rzq/1 rzq/1 rzq/1 rzq/2 rzq/2 rzq/2 rzq/2 rzq/2 rzq/2 rzq/2 rzq/4 rzq/3 rzq/3 rzq/3 rzq/3 rzq/3 rzq/3 rzq/6 rzq/4 rzq/4 rzq/4 rzq/4 rzq/4 rzq/4 rzq/8 rzq/6 rzq/6 rzq/6 rzq/6 rzq/6 rzq/6 rzq/12 r tt 120 pd 240 r tt 120 pu 240 r tt 60 pd 120 r tt 60 pu 240 r tt 40 pd 80 r tt 40 pu 80 r tt 30 pd 60 r tt 30 pu 60 r tt 20 pd 40 r tt 20 pu 40 120 60 40 30 20
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 37 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product odt sensitivity if either the temperature or voltage changes after i/o calibration, the tolerance limits listed in table 29 can be expected to widen according to tables 31 and 32. symbol min max units r tt rzq/(2, 4, 6, 8, 12) t able 31: odt s ensitivity d efinition 1.6 + dr tt dt x [dt] + dr tt dv x [dv] 0.9 - dr tt dt x dr tt dv x [dv] t able 32 - odt t emperature & v oltage s ensitivity change min max units dr tt dt dr tt dv 0 0 1.5 0.15 0 0 odt loading differs from that used in ac timing measurements. two param- eters de ne when odt turns on or off synchronously, two de ne when odt turns on or off asynchronously and, another de nes when odt turns on or off dynamically. table 33 outlines and provides de nition and measurement reference settings for each parameter. odt turn-on time begins when the output leaves high-z and odt resis- tance begins to turn on. odt turn-off time begins when the output leaves low-z and odt resistance begins to turn-off. odt timing definitions timing reference point dq, dm dqs, dqs# dut v ref v tt = v ss q v cc q/2 zq rzq = 240 v ss q r tt = 25 ck, ck# f igure 15 - odt t iming r eference l oad
ck ck # t aon v ss q dq, dm dqs, dqs# begin point: rising edge of ck - ck# defined by the end point of odtl on v sw 1 end point: extrapolated point at v ss q t sw 1 t sw 2 ck ck # v cc q/2 t aof end point: extrapolated point at v rtt _ nom v rtt _ nom v ss q t aon t aof v sw 2 v sw 2 v sw 1 t sw 1 t sw 1 begin point: rising edge of ck - ck# defined by the end point of odtl off logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 38 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product p ackage o utline d imensions symbol begin point de nition end point de nition figure t aon t aof t aon pd t aof pd t adc t able 33: odt t iming d efinitions figure 25 on page 60 figure 25 on page 60 figure 26 on page 61 figure 26 on page 61 figure 27 on page 62 extrapolated point at vssq extrapolated point at vr tt _norm extrapolated point at vssq extrapolated point at vr tt _nom extrapolated points at vr tt _wr and vr tt _nom rising edge of ck-ck\ de ned by the end point of odtl on rising edge of ck-ck\ de ned by the end point of odtl off rising edge of ck-ck\ with odt rst being registered high rising edge of ck-ck\ with odt rst being registered low rising edge of ck-ck\ de ned by the end point of odtlcnw, odtlcwn4, or odtlcwn8 p ackage o utline d imensions parameter r tt _norm setting r tt _wr_setting vsw1 vsw2 t aon t aof t aon pd t aof pd t adc t able 34: r eference s ettings for odt t iming m easurements 100mv 200mv 100mv 200mv 100mv 200mv 100mv 200mv 300mv 50mv 100mv 50mv 100mv 50mv 100mv 50mv 100mv 200mv n/a n/a n/a n/a n/a n/a n/a n/a rzq/2 (120 ) rzq/4 (60 ) rzq/12 (20 ) rzq/4 (60 ) rzq/12 (20 ) rzq/4 (60 ) rzq/12 (20 ) rzq/4 (60 ) rzq/12 (20 ) rzq/12 (20 ) measured f igure 16 - t aon and t aof d efinitions odt timing definitions
ck ck # t aonpd v ss q dq, dm dqs, dqs# begin point: rising edge of ck - ck# with odt first registered high v sw 1 end point: extrapolated point at v ss q t sw 2 ck ck # v cc q/2 t aofpd end point: extrapolated point at v rtt _ nom v rtt _ nom v ss q t aonpd t aofpd t sw 1 t sw 2 t sw 1 v sw 2 v sw 2 v sw 1 begin point: rising edge of ck - ck# with odt first registered low logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 39 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product odt characteristics f igure 17 - t aonpd and t aofpd d efinition f igure 18 - t adc d efinition ck ck # t adc dq, dm dqs, dqs# end point: extrapolated point at v rtt _ nom t sw 21 t adc end point: extrapolated point at v rtt _ wr v cc q/2 v ss q v rtt _ nom v rtt _ wr v rtt _ nom t sw 11 v sw 1 v sw 2 t sw 12 t sw 22 begin point: rising edge of ck - ck# defined by the end point of odtl cnw begin point: rising edge of ck - ck# defined by the end point of odtl cnw 4 or odtl cnw 8
r on pu r on pd output driver to other circuitry such as rcv, . . . chip in drive mode v cc q v ss q i pu i pd i out v out dq logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 40 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product output driver impedance f igure 19 - o utput d river 34 o hm o utput d river i mpedance the 34 driver (mr1[5,1]=01) is the default driver. unless otherwise stated, all timings and speci cations listed herein apply to the 34 driver only. its impedance r on is de ned by the value of the external reference resistor rzq as follows: r on 34=rzq/7 (with nominal rzq=240 1%) and is actu- ally 34.3 1%. the 34 output driver impedance characteristics are listed in table 35. p ackage o utline d imensions mr1[5,1] r on resistor v out min typ max units notes 0, 1 t able 35: 34 d river i mpedance c haracteristics rzq/7 rzq/7 rzq/7 rzq/7 rzq/7 rzq/7 % 1 1 1 1 1 1 1, 2 0.2/vccq 0.5/vccq 0.8/vccq 0.2/vccq 0.5/vccq 0.8/vccq 0.5/vccq 34.3 r on 34 pd r on 34 pu 0.6 0.9 0.9 0.9 0.9 0.6 -10 1.0 1.0 1.0 1.0 1.0 1.0 n/a 1.1 1.1 1.4 1.4 1.1 1.1 10 pull-up/pull-down mismatch (mm pupd ) notes: tolerance limits assume rzq of 240 (1%) and are applicable after proper zq calibration has been performed at a stable temperature and voltage 1. (vccq = vcc, vssq = vss). refer to ?34 ohm drive sensitivity? if either the temperature or the voltage changes after calibrati on measurement de nition for mismatch between pull-up and pull-down (mm 2. pupd ). mearure both r onpu and r onpd at 0.5 x vccq: mm pud = r on nom r onpu - r onpd
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 41 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product 34 o hm output driver impedance 34 o hm d river the 34 driver?s current range has been calculated and summarized in table 37 for vcc=1.5v, table 38 for vcc=1.575v and table 39 for v cc=1.425v. the individual pull-up and pull-down resistors (ron34pd and ron34pu) are de ned as follows with the impedance calculations listed in table 36. ? r on 34pd=(v out )/[i out ]: ron34pu is turned off ? r on 34pu=(vccq-v out )/[i out ]: ron34pd is turned off p ackage o utline d imensions mr1[5,1] ron resistor vout min typ max units 0, 1 t able 36: 34 d river p ull -u p and p ull -d own i mpedance c alculations 0.2/vccq 0.5/vccq 0.8/vccq 0.2/vccq 0.5/vccq 0.8/vccq 34.3 r on 34 pd r on 34 pu 2.04 30.5 30.5 30.5 30.5 20.4 34.3 34.3 34.3 34.3 34.3 34.3 38.1 38.1 48.5 48.5 38.1 38.1 242.4 34.6 240 34.3 237.6 33.9 r on min typ max units rzq = 240 1% rzq = (240 1%)/7 p ackage o utline d imensions mr1[5,1] r on resistor v out min typ max units 0, 1 ma ma ma ma ma ma i ol @ 0.2 x vccq i ol @ 0.5 x vccq i ol @ 0.8 x vccq i ol @ 0.2 x vccq i ol @ 0.5 x vccq i ol @ 0.8 x vccq 34.3 r on 34 pd r on 34 pu 15.5 25.8 41.2 41.2 25.8 15.5 9.2 23 36.8 36.8 23 9.2 8.3 20.7 26 26 20.7 8.3 t able 38: 34 d river i oh /i ol c haracteristics : v cc =v cc q=1.575v p ackage o utline d imensions mr1[5,1] r on resistor v out min typ max units 0, 1 ma ma ma ma ma ma i ol @ 0.2 x vccq i ol @ 0.5 x vccq i ol @ 0.8 x vccq i ol @ 0.2 x vccq i ol @ 0.5 x vccq i ol @ 0.8 x vccq 34.3 r on 34 pd r on 34 pu 14.7 24.6 39.3 39.3 24.6 14.7 8.8 21.9 35 35 21.9 8.8 7.9 19.7 24.8 24.8 19.7 7.9 t able 37: 34 d river i oh /i ol c haracteristics : v cc = v cc q = 1.5v
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 42 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product 34 o hm output driver impedance p ackage o utline d imensions mr1[5,1] r on resistor v out min typ max units 0, 1 ma ma ma ma ma ma i ol @ 0.2 x vccq i ol @ 0.5 x vccq i ol @ 0.8 x vccq i ol @ 0.2 x vccq i ol @ 0.5 x vccq i ol @ 0.8 x vccq 34.3 r on 34 pd r on 34 pu 14 23.3 37.3 37.3 23.3 14 8.3 20.8 33.3 33.3 20.8 8.3 7.5 18.7 23.5 23.5 18.7 7.5 t able 39: 34 d river i oh /i ol c haracteristics : v cc =v cc q=1.425v 34 output driver sensitivity if either the temperature or voltage changes after zq calibration, the tolerance limits listed in table 35 can be expected to w iden according to table 40 and 41. symbol min max units r on @ 0.8 x vccq r on @ 0.5 x vccq r on @ 0.2 x vccq rzq/7 rzq/7 rzq/7 t able 40: 34 o utput d river s ensitivity d efinition 1.1 - dr on dth x [ ? t] + dr on dvh x [ ? v] 1.1 - dr on dtm x [ ? t] + dr on dvm x [ ? v] 1.1 - dr on dtl x [ ? t] + dr on dvl x [ ? v] 0.9 - dr on dth x [ ? t] + dr on dvh x [ ? v] 0.9 - dr on dtm x [ ? t] + dr on dvm x [ ? v] 0.9 - dr on dtl x [ ? t] + dr on dvl x [ ? v] change min max units dr on dtm dr on dvm dr on dtl dr on dvl dr on dth dr on dvh %/c %/mv %/c %/mv %/c %/mv t able 41: 34 o utput d river v oltage and t emperature s ensitivity 1.5 0.13 1.5 0.13 1.5 0.13 0 0 0 0 0 0
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 43 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product alternative 40 ohm driver p ackage o utline d imensions mr1[5,1] r on resistor v out min typ max units notes 0, 1 t able 42 - 40 d river i mpedance c haracteristics rzq/6 rzq/6 rzq/6 rzq/6 rzq/6 rzq/6 % 1 1 1 1 1 1 1, 2 0.2/vccq 0.5/vccq 0.8/vccq 0.2/vccq 0.5/vccq 0.8/vccq 0.5/vccq 40.0 r on 40 pd r on 40 pu 0.6 0.9 0.9 0.9 0.9 0.6 -10 1.0 1.0 1.0 1.0 1.0 1.0 n/a 1.1 1.1 1.4 1.4 1.1 1.1 10 pull-up/pull-down mismatch (mm pupd ) notes: tolerance limits assume rzq of 240 (1%) and are applicable after proper zq calibration has been performed at a stable temperature and voltage 1. (vccq = vcc, vssq = vss). refer to ?40 ohm drive sensitivity? if either the temperature or the voltage changes after calibrati on measurement de nition for mismatch between pull-up and pull-down (mm 2. pupd ). mearure both r on pu and r on pd at 0.5 x vccq: mm pupd = r on nom r onpu - r onpd x 100 40 output driver sensitivity if either the temperature or voltage changes after i/o calibration, the tolerance limits listed in table 42 can be expected to widen according to table 43 and 44. symbol min max units r on @ 0.8 x vccq r on @ 0.5 x vccq r on @ 0.2 x vccq rzq/6 rzq/6 rzq/6 t able 43: 40 o utput d river s ensitivity d efinition 1.1 - dr on dth x [ ? t] + dr on dvh x [ ? v] 1.1 - dr on dtm x [ ? t] + dr on dvm x [ ? v] 1.1 - dr on dtl x [ ? t] + dr on dvl x [ ? v] 0.9 - dr on dth x [ ? t] + dr on dvh x [ ? v] 0.9 - dr on dtm x [ ? t] + dr on dvm x [ ? v] 0.9 - dr on dtl x [ ? t] + dr on dvl x [ ? v]
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 44 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product alternative 40 ohm driver change min max units dr on dtm dr on dvm dr on dtl dr on dvl dr on dth dr on dvh %/c %/mv %/c %/mv %/c %/mv t able 44: 40 o utput d river v oltage and t emperature s ensitivity 1.5 0.15 1.5 0.15 1.5 0.15 0 0 0 0 0 0 output characteristics and operating conditions the sdram uses both single-ended and differential output drivers. the single-ended output driver is summarized in table 45 whi le the differential output driver is summarized in table 46. p ackage o utline d imensions parameter/condition symbol min max units notes output leakage current: dq are disabled; 0v v out vccq; odt is disabled; odt is high output slew rate: single-ended; for rising and falling edges, measure between v ol (ac) = v ref - 0.1 x vccq and v oh (ac) = v ref + 0.1 x vccq single-ended dc high-level output voltage single-ended dc mid-point level output voltage single-ended dc low-point level output voltage single-ended dc high-point level output voltage single-ended dc low-point level output voltage delta r on between pull-up and pull-down for dq/dqs test load for ac timing and output slew rates ua v/ns v v v v v % 1 1, 2, 3, 4 1, 2, 5 1, 2, 5 1, 2, 5 1, 2, 3, 6 1, 2, 3, 6 1, 7 3 t able 45: s ingle -e nded o utput d river characteristics 5 6 10 -5 2.5 -10 i oz srqse v oh (dc) v om (dc) v ol (dc) v oh (ac) v ol (ac) mm pupd 0.8 x vccq 0.5 x vccq 0.2 x vccq vtt + 0.1 x vccq vtt - 0.1 x vccq output to v tt (vccq/2) via 25 resistor see table 35 on page 40 iv curve linearity. do not use ac test load. 5. see table 47 on page 47 for output slew rate. 6. see table 35 on page 40 for additional information. 7. see figure 29 on page 66 for an example of a single-ended output 8. signal. notes: rzq of 240 (1%) with rzq/7 enabled (default 34 driver) and is appli- 1. cable after proper zq calibration has been performed at a stable tem- perature and voltage (vccq = vcc, vssq = vss). v 2. tt = vccq/2 see figure 31 on page 68 for the test load con guration. 3. the 6v/ns maximum is applicable for a single dq signal when it is switch- 4. ing from either high to low or low to high while the remaining dq signals in the same byte lane are combinations, the maximum limit of 6v/ ns maximum is reduced to 5v/ns.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 45 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product p ackage o utline d imensions parameter/condition symbol min max units notes output leakage current: dq are disabled; 0v v out vccq; odt is high output slew rate: differential; for rising and falling edges, measure between v ol diff(ac) = - 0.2 x vccq and v oh (ac) = + 0.2 x vccq output differential cross-point voltage differential high-level output voltage differential low-level output voltage delta r on between pull-up and pull-down for dq/dqs test load for ac timing and output slew rates ua v/ns mv v v % 1 1 1, 2, 3 1, 4 1, 4 1, 5 3 t able 46: d ifferential o utput d river characteristics 5 12 v ref +150 10 -5 5 v ref -150 -10 i oz srqdiff v ox (ac) v oh diff(ac) v ol diff(ac) mm pupd + 0.2 x vccq - 0.2 x vccq output to v tt (vccq/2) via 25 resistor see table 48 on page 65 for the output slew rate. 4. see table 35 on page 58 for additional information. 5. see figure 30 on page 67 for an example of a differential output 6. signal. notes: rzq of 240 (1%) with rzq/7 enabled (default 34 driver) and is appli- 1. cable after proper zq calibration has been performed at a stable tem- perature and voltage (vccq = vcc, vssq = vss). v 2. ref = vccq/2 see figure 31 on page 68 for the test load con guration. 3. f igure 20 - dq o utput s ignal v oh ( ac ) min output max output v ol ( ac )
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 46 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 21 - d ifferential o utput s ignal v oh ( diff ) min output max output v ol ( diff ) v ox ( ac ) max v ox ( ac ) min x x x x output characteristics and operating conditions reference output load figure 22 represents the effective reference load of 25 used in de ning the relevant device ac timing parameters (except odt reference timing) as well as the output slew rate measurements. it is not intended to be a precise representation of a particular system environment or a depic tion of the actual load presented by any speci c industry test system/apparatus. system designers should use ibis or other simulation tools to correlate the timing reference load presented or exhibited on the system or system environment. f igure 22 - r eference o utput l oad for ac t iming and o utput s lew r ate timing reference point dq dqs dqs# dut v ref v tt = v cc q/2 v cc q/2 zq rzq = 240 v ss r tt = 25
p ackage o utline d imensions output edge from to calculation dq t able 47: s ingle -e nded o utput s lew r ate output slew rate (linear signals) rising falling measured v ol (ac) v oh (ac) v oh (ac) v ol (ac) v oh (ac) - v ol (ac) ? trse v oh (ac) - v ol (ac) ? tfse logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 47 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product slew rate definitions for single-ended output signals the single-ended output driver is summarized in table 45. with the reference load for timing measurements, the output slew-rat e for falling and rising edges is de ned and measured between v ol (ac) and v oh (ac) for single-ended signals as indicated in table 47 and figure 23. f igure 23 - n ominal s lew r ate d efinition for s ingle -e nded o utput s ignals

p ackage o utline d imensions output edge from to calculation dqs, dqs\ t able 48: d ifferential o utput s lew r ate d efinition output slew rate (linear signals) rising falling measured v ol diff(ac) v oh diff(ac) v oh diff(ac) v ol diff(ac) v oh diff(ac) - v ol diff(ac) ? trdiff v oh diff(ac) - v ol diff(ac) ? tfdiff logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 48 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product slew rate definitions for differential output signals the differential output driver is summarized in table 46. with the reference load for timing measurements, the output slew rat e for falling and rising edges is de ned and measured between v ol (ac) and v oh (ac) for differential signals, as shown in table 48 and figure 33. f igure 24 - n ominal d ifferential o utput s lew r ate d efinition for dqs, dqs#

logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 49 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product p ackage o utline d imensions parameter symbol min max min max min max units notes activate to internal read or write delay time precharge command period activate-to-activate or refresh command period activate-to-precharge command period cl=5 cl=6 cl=8 cl=10 supported cl settings supported cwl settings 1 2 3 3 2 3 3 3 2,3 3 3 3 2,3 t able 49: s peed b ins -25 (ddr3-800) -19 (ddr3-1066) -15 (ddr3-1333) [cwl=2.5; 6-6-6] [cwl=1.875; 8-8-8] [cwl=1.5; 10-10-10] t rcd t rp t rc t ras t ck (avg) t ck (avg) t ck (avg) t ck (avg) t ck (avg) t ck (avg) t ck (avg) t ck (avg) t ck (avg) t ck (avg) t ck (avg) t ck (avg) 15 15 52.5 37.5 3 2.5 5,6 5, 6, 8 5, 6, 8, 10 - - - 60ms 3.3 3.3 15 15 52.5 37.5 3 2.5 1.875 - - - 60ms 3.3 3.3 <2.5 15 15 51 36 3 2.5 1.875 1.5 - - - 60ms 3.3 3.3 <2 <1.875 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ck ck cwl=5 cwl=6 cwl=7 cwl=5 cwl=6 cwl=7 cwl=5 cwl=6 cwl=7 cwl=5 cwl=6 cwl=7 5 5, 6 5, 6, 7 reserved ( lled blocks) settings are not allowed. 3. notes: t 1. refi depends on t oper the cl and cwl setting result in 2. t ck requirements. when making a selection of t ck, both cl and cwl requirement settings need to be ful- lled.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 50 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 50 ( sheet 1 of 6) - e lectrical c haracteristics and ac o perating conditions min max min max min max 8 7800 8 7800 8 7800 9,42 8 3900 8 3900 8 3900 9,42 8 2900 8 2900 8 2900 9,42 ns 10,11 0.47 0.53 0.47 0.53 0.47 0.53 ck 12 0.47 0.53 0.47 0.53 0.47 0.53 ck 12 -100 100 -90 90 -80 80 ps 13 -90 90 -80 80 -70 70 ps 13 ps ps 16 ps 16 -147 147 -132 132 -118 118 ps 17 -175 175 -157 157 -140 140 ps 17 -194 194 -175 175 -155 155 ps 17 -209 209 -188 188 -168 168 ps 17 -222 222 -200 200 -177 177 ps 17 -232 232 -209 209 -186 186 ps 17 -241 241 -217 217 -193 193 ps 17 -249 249 -224 224 -200 200 ps 17 -257 257 -231 231 -205 205 ps 17 -263 263 -237 237 -210 210 ps 17 -269 269 -242 242 -215 215 ps 17 units notes [cwl=1.5; 10-10-10] symbol parameter -25 (ddr3-800) -19 (ddr3-1066) [cwl=2.5; 6-6-6] [cwl=1.875; 8-8-8] -15 (ddr3-1333) 11 cycles 12 cycles 0.43 - 0.43 - t errnper min = (1+0.68ln[n]) x t jitper min t errnper max = (1+0.68ln[n]) x t jitper max 0.43 - 0.43 - 14 t ck (avg) 15 ps 17 180 160 140 180 160 t errnper t jitcc t jitcc, lck t err6perr t err7perr t err8perr n = 13, 14 49, 50 cycles t err2perr t err3perr t err4perr t err5perr 200 t err9perr t err10perr t err11perr t err12perr cumulave error across 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles 9 cycles 10 cycles clock period jitter cycle-to-cycle jitter dll locked dll locking dll locked dll locking clock absolute period clock absolute high pusle width clock absolute low pulse width t clk (abs) t ckdll_dis t cl (avg) t ch (abs) t cl (abs) clock period average: dll enable mode high pulse width average low pulse width average clock period average: dll disable mode tc = 85?c to 105?c 0.43 - t jitper t jitper, lck t ck (avg) ns - 0.43 t ck (avg) min= t ck (avg) min+ t jitper min; max= t ck (avg)max+ t jitper max tc = 0?c to <85?c tc = >105?c to 125?c t ch (avg) see speed bin table (#49) for tck range allowed
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 51 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 50 ( sheet 2 of 6) - e lectrical c haracteristics and ac o perating conditions min max min max min max 75 - 25 - - - ps 18,19 250 - 200 - - - ps 19,20 125 - 75 - 30 - ps 18,19 275 - 250 - 180 - ps 19,20 150 - 100 - 65 - ps 18,19 250 - 200 - 165 - ps 19,20 600 - 490 - 400 - ps 41 - 200 - 150 - 125 ps -800 400 -600 300 -500 250 ps 22,23 - 400 - 300 - 250 ps 22,23 -0.25 0.25 -0.25 0.25 -0.25 0.25 ck 25 0.45 0.55 0.45 0.55 0.45 0.55 ck 0.45 0.55 0.45 0.55 0.45 0.55 ck 0.2-0.2-0.2- ck25 0.2 - 0.2 - 0.2 - ck 25 0.9-0.9-0.9- ck 0.3-0.3-0.3- ck -400 400 -300 300 -255 255 ps 23 0.38 - 0.38 - 0.4 - ck 21 0.38 - 0.38 - 0.4 - ck 21 -800 400 -600 300 -500 250 ps 22,23 - 400 - 300 - 250 ps 22,23 0.9 note 24 0.9 note 24 0.9 note 24 ck 23,24 0.3 note 27 0.3 note 27 0.3 note 27 ck 23,27 data setup me to dqs, dqs\ t ds ac150 dq input timing data hold me from dqs, dqs\ vref @ 1v/ns data setup me to dqs, dqs\ t ds ac175 base (speci?caon) [cwl=1.875; 8-8-8] vref @ 1v/ns base (speci?caon) vref @ 1v/ns base (speci?caon) dq high-a me from ck, ck\ dqs, dqs\ differential read postamble t rpst dqs, dqs\ differential output high me units notes dq low-z me from ck, ck\ dq strobe input timing dqs, dqs\ differential write postamble parameter -25 (ddr3-800) -19 (ddr3-1066) -15 (ddr3-1333) [cwl=2.5; 6-6-6] [cwl=1.5; 10-10-10] symbol dqs, dqs\ falling setup to ck, ck\ rising t dss dq ouput timing dqs, dqs\ to dq skew, per access dq output hold me from dqs, dqs\ t dqss dqs, dqs\ differential input low pulse width t wpst dqs,dqs\ rising to ck, ck\ rising t dqsl dqs, dqs\ differential input high pulse width t dqsh dqs, dqs\ differential read preamble t rpre dqs, dqs\ falling hold from ck, ck\ rising t dsh dqs, dqs\ differential write preamble t wpre dq strobe output timing 1 t qsh dqs, dqs\ differential output low me t qsl 26 dqs, dqs\ rising to/from rising ck, ck\ t dqsck dqs, dqs\ high-z me (rl+bl/2) t hz (dqs) dqs, dqs\ low-z me (rl-1) t lz (dqs) 10 1 10 ns dqs, dqs\ rising to/from rising ck, ck\ when dll is disabled t dqsk dll_dis 10 1 t dh ac100 minimum data pulse width t dipw t qh 0.38 - t dqsq - 0.38 - tck (avg) 21 t hz (dq) t lz (dq) 0.38
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 52 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 50 ( sheet 3 of 6) - e lectrical c haracteristics and ac o perating conditions min max min max min max 512 - 512 - 512 - ck 28 200 - 125 - 65 - ps 29,30 375 - 300 - 240 - ps 20,30 350 - 275 - 190 - ps 29,30 500 - 425 - 340 - ps 20,30 275 - 200 - 140 - ps 29,30 375 - 300 - 240 - ps 20,30 900 - 780 - 620 - ps 41 ns 31 ns 31 ns 31,32 ns 31 40 - 37.5 - 30 - ns 31 50 - 50 - 45 - ns 31 ck ck ck ck multipurpose register read burst end to mode register set for mulpurpose register exit t mprr min = 1ck; max = n/a ck min = 4ck; max = n/a min = greater of 12ck or 15ns; max = n/a mode register set command cycle me t mrd min = greater of 4ck or 7.5ns; max = n/a min = 4ck; max = n/a auto precharge write recovery + precharge me t dal min = wr + t rp/ t ck (avg); max = n/a ck cas\-to-cas\ command delay t ccd min = 15ns; max = n/a delay from start of internal write transacon to internal read command t wtr min = greater of 4ck or 7.5ns; max = n/a ck 31,32,33 ck 31,34 write recovery me t wr mode register set command update delay t mod four activate windows for 2kb page size four activate windows for 1kb page size t faw read-to-prechare me t rtp notes [cwl=2.5; 6-6-6] [cwl=1.875; 8-8-8] [cwl=1.5; 10-10-10] symbol parameter -25 (ddr3-800) -19 (ddr3-1066) -15 (ddr3-1333) units command and address timing ctrl, cmd, addr setup to ck, ck\ base (speci?caon) vref @ 1v/ns t is ac175 ctrl, cmd, addr setup to ck, ck\ base (speci?caon) t is ac150 vref @ 1v/ns ctrl, cmd, addr hold to ck, ck\ base (speci?caon) t ih dc100 vref @ 1v/ns dll locking me t dllk see "speed bin table (#49) for trcd see "speed bin table (#49) for trp see "speed bin table (#49) for tras minimum ctrl, cmd, addr pulse width t ipw activate to internal read or write delay t rcd precharge command period t rp 1kb page size min=greater of 4ck or 10ns min=greater of 4ck or 7.5ns activate-to-precharge command period t ras activate-to-activate command period t rcd see "speed bin table (#49) for trc ck 31 min=greater of 4ck or 6ns ck 31 activate-to-activate minimum command period 2kb page size t rrd min=greater of 4ck or 10ns min=greater of 4ck or 6ns
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 53 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 50 ( sheet 4 of 6) - e lectrical c haracteristics and ac o perating conditions min max min max min max 256 - 256 - 256 - ck 64 - 64 - 64 - ck ck ms ns 35 ms 36 ms 36 ms 36 s 36 s 36 s 36 valid clocks aer self refresh entry or power-down entry t cksre min = greater of 5ck or 10ns; max = n/a ck valid clocks before self refresh exit, power-down exit, or reset exit t cksrx min = greater of 5ck or 10ns; max = n/a ck exit self refresh to commands requiring a locked dll t xsdll min = t dllk (min); max = n/a ck 28 minimum cke low pulse width for self refresh entry to self refresh exit ming t ckesr min = t cke (min) + ck; max = n/a ck self refresh timing exit self refresh to commands not requiring a locked dll t xs min = greater of 5ck or t rfc + 10ns; max = n/a ck maximum refresh period/interval tc 85?c t refi 7.8 tc >85?c 105?c 3.9 tc >105?c 125?c 2.9 tc 85?c - tc >105?c 125?c 64 32 24 tc >85?c 105?c maximum refresh period begin power supply ramp to power supplies stable t vddpr min = n/a; max = 200 ms refresh-to-activate or refresh command period t rfc min = 110; max = 9 x t refi ns refresh timing reset\ low to power supplies stable t rps min = 0; max = 200 reset\ low to i/o and rtt high-z t ioz min = n/a; max = 200 zqcs command: short calibraon time t zqcs exit reset from cke high to a valid command t xpr min = greater of 5ck or trfc + 10ns; max = n/a inializaon and reset timing - 512 - 512 - ck zqcl command: long calibraon me power-up and reset operaon normal operaon t zqinit t zqoper 512 notes [cwl=2.5; 6-6-6] [cwl=1.875; 8-8-8] [cwl=1.5; 10-10-10] symbol calibraon timing parameter -25 (ddr3-800) -19 (ddr3-1066) -15 (ddr3-1333) units
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 54 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 50 ( sheet 5 of 6) - e lectrical c haracteristics and ac o perating conditions min max min max min max ck ck ck ck 37 ck ck ck ck min = greater of 3ck or 7.5ns; max = n/a min = greater of 3ck or 6ns; max = n/a ck 28 min = greater of 10ck or 24ns; max = n/a bl8 (otf, mrs) bc4otf t wrapden min = wl + 4 + wr + 1 ck min = wl + 2 + wr + 1 bl8 (otf, mrs) bc4otf t wrpden t wrpden min = wl + 4 + t wr/ t ck (avg) ck t wrapden bc4mrs min = wl + 2 + t wr/ t ck (avg) write with auto precharge command to power-down entry bc4mrs dll on, any valid command, or dll o? to commands not requiring dll locked t xp read/read with auto precharge commant to power-down entry t rdpden min = rl + 4 + 1 ck write command to power- down entry refresh command to power-down entry t refpden min = 1 mrs command to power-down entry t mrspden min = t mod (min) t actpden min = 1 precharge/precharge all command to power-down entry t prpden min = 1 ck command pass disable delay t cpded min = 1; max = n/a power-down entry to power-down exit ming t pd min = tcke (min); max = 60ms power-down entry period: odt eher synchronous or asynchronous pde greater of tanpd or trfc - refresh command to cke low me ck ck power-down exit period: odt either synchronous or asynchronous pdx t anpd + t xpdll ck greater of 3ck or 7.5ns greater of 3ck or 5.625ns greater of 3ck or 5.625ns begin power-down period prior to cke registered high t anpd wl - 1ck power-down timing power-down entry minimum timing power-down exit timing precharge power-down with dll o? to command requiring dll locked t xpdll cke min pulse width t cke (min) activate command to power-down entry ck parameter -25 (ddr3-800) -19 (ddr3-1066) -15 (ddr3-1333) units notes [cwl=2.5; 6-6-6] [cwl=1.875; 8-8-8] [cwl=1.5; 10-10-10] symbol
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 55 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 50 ( sheet 6 of 6) - e lectrical c haracteristics and ac o perating conditions min max min max min max ck 38 ck 40 -400 400 -300 300 -250 250 ps 23,38 0.3 0.7 0.3 0.7 0.3 0.7 ck 39,40 ck ck ck 0.3 0.7 0.3 0.7 0.3 0.7 ck 39 40 - 40 - 40 - ck 25 - 25 - 25 - ck 090909ns 020202ns write leveling output error t wloe t wls t wlh 195 - ps write leveling output delay t wlo write leveling hold from rising dqs, dqs\ crossing to rising ck, ck\ crossing 325 - 245 dqs; dqs\ delay t wldqsen write leveling setup from rising ck, ck\ crossing to rising dqs, dqs\ crossing 325 - 245 - 195 - 6ck + odtl off rtt dynamic change skew t adc first dqs, dqs\ rising edge t wlmrd ps - rtt_nom-to=rtt_wr change skew odtl cnw wl - 2ck rtt_wr-to-rtt_nom change skew - bc4 odtl cnw4 4ck + odtl off rtt_wr-to-rtt_nom change skew - bc8 odtl cnw8 odt high me without write command or with write command and bc8 odt h8 min = 6; max = n/a ck odt high me without write command or with write command and bc4 odt h4 min = 4; max = n/a ck ns 38 asynchronous rtt turn-off delay (power-down with dll off) t aofpd min = 2; max = 8.5 ns 40 t aon rtt turn-off from odtl off reference t aof asynchronous rtt turn-on delay (power-down with dll off) t aonpd min = 2; max = 8.5 odt timing dynamic odt timing write leveling timing rtt synchronous turn-on delay odtl on rtt synchronous turn-off delay odtl o? rtt turn-on from odtl on reference parameter -25 (ddr3-800) -19 (ddr3-1066) -15 (ddr3-1333) units notes [cwl=2.5; 6-6-6] [cwl=1.875; 8-8-8] [cwl=1.5; 10-10-10] symbol
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 56 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product n otes parameters are applicable with 0 ? c tc +95 ? c and vcc/vccq = + 1. 1.5v 0.075v. all voltages are referenced to vss. 2. output timings are only valid for r 3. on 34 output buffer selection. unit 4. t ck (avg) represents the actual t ck (avg) of the input clock under operation. unit ck represents one clock cycle of the input clock, counting the actual clock edges. ac timing and i 5. cc tests may use a v il -to-v ih swing of up to 900mv i the test environment, but input timing is still referenced to v ref (except t is, t ih, t ds, and t dh use the ac/dc trip points and ck, ck\ and dqs, dqs\ use their crossing points). the minimum slew rate for the input signals used to test the device is 1v/ns for single-ended inputs and 2v/ ns for differential inputs in the range between v il (ac) and v ih (ac). all timings that use time-based values (ns, s, ms) should use 6. t ck (avg) to determine the correct number of clocks (table 50 uses ck or ck (avg) interchangeably). in the case of non-interger results, all minimum limits are to be rounded up to the nearest whole integer. the use of strobe or dqsdiff refers to the dqs and dqs\ differen- 7. tial crossing point when dqs is the rising edge. the use of clock or ck refers to the ck and ck\ differential crossing point when ck is the rising edge. this output load is used for all ac timing (except odt reference timing) 8. and slew rates. the actual test load may be different. the output signal voltage reference point is vccq/2 for single-ended signals and the crossing point for differential signals. when operating in dll disable mode, logic devices, inc. (ldi) does 9. not warrant compliance with normal mode timings or functionality. the clock?s 10. t ck (avg) is the average clock over any 200 consecutive clocks and t ck (avg) min is the smallest clock rate allowed, with the exception of a deviation due to clock jitter. input clock jitter is allowed provided it does not exceed values speci ed and must be of a random gaussian distribution in nature. spread spectrum is not included in the jitter speci cation values. how- 11. ever, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20-60khz with and additional 1% of t ck (avg) as a long-term jitter component; however, the spread-spectrum may not use a clock rate below t ck (avg) min. the clock?s 12. t ch (avg) and t cl (avg) are the average half clock period over any 200 consecutive clocks and is the smallest clock half period allowed, with the exception of values speci ed and must of a random gaussian distribution in nature. the period jitter ( 13. t jitper) is the maximum deviation in the clock period from the average or nominal clock. it is allowed in either the positive or negative direction. t 14. ch (abs) is the absolute instantaneous clock high pulse width as mea- sured from one rising edge to the following falling edge. t 15. cl (abs) is the absolute instantaneous clock low pulse width as mea- sured from one falling edge to the following rising edge. the cycle-to-cycle jitter ( 16. t jitcc) is the amount the clock period can deviate from one cycle to the next. it is important to keep cycle-to-cycle jitter at a minimum during the dll locking time. the cumulative jitter error ( 17. t errnper), where n is the number of clocks between 2 and 50, is the amount of clock time allowed to accu- mulate consecutively away from the average clock over n number of clock cycles. t 18. ds (base) and t dh (base) values are for a single-ended 1v/ns dq slew rate and 2v/ns for differential dqs, dqs\ slew rate. these parameters are measured from a data signal (dm, dq0, dq1 ? 19. dqn and so forth) transition edge to its respective data strobe signal (dqs, dqs\) crossing. the setup and hold times are listed converting the base speci cation 20. values (to which derating tables apply) to v ref when the slew rate is 1v/ns. these values, with a slew rate of 1v/ns are for reference only. when the device is operated with input clock jitter, this parameter 21. needs to be derated by the actual t jitper (larger of t jitper (min) or t jitper (max) of the input clock (output deratings are relative to the sdram input clock). single-ended signal parameter. 22. the sdram output timing is aligned to the nominal or average clock. 23. most output parameters must be derated by the actual jitter error when input clock jitter is present, even when within speci cation. this results in each parameter becoming larger. the following parameters are required to be derated by subtracting t err10per (max); t dqsck (min), t lz (dqs) max, t lz (dq) max, and t aon (max). the parame- ter t rpre (min) is derated by subtracting t jitper (max), while t rpre (max) is derated by t jitper (min). the maximum preamble is bound by 24. t lzdqs (max). these parameters are measured from a data strobe signal (dqs, dqs\) 25. crossing to its respective clock signal (ck, ck\) crossing. the speci- cation values are not affected by the amount of clock jitter applied, as these are relative to the clock signal crossing. these parameters should be met whether clock jitter is present or not. the 26. t dqsck dll_dis parameter begins cl + al - 1 cycles after the read command. the maximum postamble is bound by 27. t hzdqs (max). commands requiring a locked dll are: read (and rdap) and syn- 28. chronous odt commands. in addition, after any change of latency t xpdll, timing must be met. t 29. is (base) and t ih (base) values are for a single-ended 1 v/ns con- trol/command/ address slew rate and 2 v/ns ck, ck# differential slew rate. these parameters are measured from a command/address signal tran- 30. sition edge to its respective clock (ck, ck\) signal crossing. the speci- cation values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the command/address. these parameters should be met whether clock jitter is present or not. for these parameters, the ddr3 sdram device supports tnparam 31. (nck) = ru ( t param [ns]/ t ck[avg][ns]), assuming all input clock
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 57 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product n otes c ontinued jitter speci cations are satis ed. for example, the device will support t nrp (nck) = ru ( t rp)/ t ck[avg]) if all input clock jitter speci cations are met. this means for ddr2-800; 6-6-6, of which t rp = 15ns, the device will support t nrp = ru ( t rp/ t ck [avg]) = 6 as long as the input clock jitter speci cations are met. that is, the precharge command at t0 and the activate command at t0+6 are valid even if six clocks are less than 15ns due to input clock jitter. during reads and writes with auto precharge, the ddr3 32. sdram will hold off the internal precharge command until t ras (min) has been satis ed. when operating in dll disable mode, the greater of 4ck or 15ns is 33. satis ed for t wr. the start of the write recovery time is de ned as follows: 34. for bl8 ( xed by mrs and otf): rising clock edge four clock ? cycles after wl. for bc4 (otf): rising clock edge four clock cycles after wl. ? for bc4 ( xed by mrs): rising clock edge two clock cycles after ? wl. reset\ should be low as soon as power starts to ramp to ensure 35. the outputs are in high-z until reset\ is low, the outputs are at risk of driving the bus and could result in excessive current, depending on the bus activity. the refresh period is 64ms when tc is less than or equal to 85 ? c. 36. this equates to an average refresh rate of 7.8124 s. however, nine refresh commands should be asserted at least once every 70.3 s. when tc is greater than 85 ? c, the refresh period is 32ms and when tc is greater than 105 ? c, the refresh period is 24ms. although cke is allowed to be registered low after a refresh 37. command when t refpden (min) is satis ed, there are cases where additional time such as t xpdll (min) is required. odt turn-on time min is when the device leaves high-z and odt 38. resistance begins to turn on. odt turn-on time maximum is when the odt resistance is fully on. the odt reference load is shown in figure 23. half-clock output parameters must derated by the actual 39. t err10per and t jitdty when input clock jitter is present. this results in each parameter becoming larger. the parameters t adc (min) and t aof(min) are each required to be derated by subtracting both ter- r10per (max) and t jitdty (max). the parameters t adc (max) and t aof (max) are required to be derated by subtracting both t er- r10per (max) and t jitdty (max). odt turn-off time minimum is when the device starts to turn off odt 40. resistance. odt turn-off time maximum is when the sdram buffer is in high-z. the odt reference load is shown in figure 24. this output load is used for odt timings (see figure 31). pulse width of an input signal is de ned as the width between the rst 41. crossing of v ref (dc) and the consecutive crossing of v ref (dc). should the clock rate be larger than 42. t rfc(min), an auto refresh command should have at least one nop command between it and another auto refresh command. additionally, if the clock rate is slower than 40ns (25mhz) all refresh commands should be fol- lowed by a precharge all command.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 58 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product command and address setup, hold, and derating the total t is (setup time) and t ih (hold time) required is calculated by adding the data sheet t is(base) and t ih (base) values (tables 51) to the ? t is and ? t ih derating values (table 52), respectively. although the total setup time for slow slew rates might be negative, a valid input signal is still required to complete the tra nsition and to reach v ih (ac)/v il (ac) (see figure 14 for input signal requirements). for slew rates which fall between the values listed in table 52 and table 53, t he derating values may be obtained by linear interpolation. setup ( t is) nominal slew rate for a rising signal is de ned as the slew rate between the last crossing of v ref (dc) and the rst crossing of v ih (ac) min. setup ( t is) nominal slew rate for a falling signal is de ned as the slew rate between the last crossing of v ref (dc) and the rst crossing of v il (ac) max. if the actual signal is always earlier than the nominal slew rate line between the shaded ?v ref (dc)-to-ac region?, use the nominal slew rate for derating value (see figure 25). if the actual signal is later than the nominal slew rate line anywhere between the shaded ?v ref (dc)-to-ac region?, the slew rate of a tangent line to the actual signal from the ac level to the dc level is used for the derating value (see figure 27). hold ( t ih) nominal slew rate for a rising signal is de ned as the slew rate between the last crossing of v il (dc) max and the rst crossing of v ref (dc). hold ( t ih) nominal slew rate for a falling signal is de ned as the slew rate between the last crossing of v ih (dc) min and the rst crossing of v ref (dc). if the actual signal is always later than the nominal slew rate line between the shaded ?dc-to-v ref (dc) region?, use the nominal slew rate for derating value (see figure 26). if the actual signal is earlier than the nominal slew rate line anywhere between the shaded ?dc-to-v ref (dc) region?, the slew rate of a tangent line to the actual signal from the dc level to the v ref (dc) level is used for the derating value (see figure 28). symbol ddr3-800 ddr3-1066 ddr3-1333 units reference t is(base)ac175 t is(base)ac150 t ih(base)dc100 v ih (ac)/v il (ac) v ih (ac)/v il (ac) v ih (ac)/v il (ac) t able 51: c ommand and a ddress s etup and h old v alues r eferenced at 1v/ ns ? ac/dc based 65 190 140 200 350 275 125 275 200 ps ps ps ? t is ? t ih ? t is ? t ih ? t is ? t ih ? t is ? t ih ? t is ? t ih ? t is ? t ih ? t is ? t ih ? t is ? t ih 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 t able 52: d erating v alues for t is/ t ih ? ac175/dc100-b ased cmd/addr slew rate v/ns 88 59 0 -2 -6 -11 -17 -35 -62 50 34 0 -4 -10 -16 -26 -40 -60 88 50 0 -2 -6 -11 -17 -35 -62 50 34 0 -4 -10 -16 -26 -40 -60 88 59 0 -2 -6 -11 -17 -35 -62 50 34 0 -4 -10 -16 -26 -40 -60 96 67 8 6 2 -3 -9 -27 -54 58 42 8 4 -2 -8 -18 -32 -52 96 67 8 6 2 -3 -9 -27 -54 66 50 16 12 6 0 -10 -24 -44 112 83 24 22 18 13 7 -11 -38 74 58 24 20 14 8 -2 -16 -36 120 91 32 30 26 21 15 -2 -30 84 68 34 30 24 18 8 -6 -26 128 99 40 38 34 29 23 5 -22 100 84 50 46 40 34 24 10 -10 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns ck, ck\ differential slew rate shaded cells indicate slew-rate combinations not supported ? t is, ? t ih derating (ps) - ac/dc-based, ac175 threshold; v ih (ac) = v ref (dc) + 175mv, v il (ac) = v ref (dc) - 175mv
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 59 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product ? t is ? t ih ? t is ? t ih ? t is ? t ih ? t is ? t ih ? t is ? t ih ? t is ? t ih ? t is ? t ih ? t is ? t ih 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 t able 53: d erating v alues for t is/ t ih ? ac150/dc100-b ased cmd/addr slew rate v/ns 75 50 0 0 0 0 -1 -10 -25 50 34 0 -4 -10 -16 -26 -40 -60 75 50 0 0 0 0 -1 -10 -25 50 34 0 -4 -10 -16 -26 -40 -60 75 50 0 0 0 0 -1 -10 -25 50 34 0 -4 -10 -16 -26 -40 -60 83 58 8 8 8 8 7 -2 -17 58 42 8 4 -2 -8 -18 -32 -52 91 66 16 16 16 16 15 6 -9 66 50 16 12 6 0 -10 -24 -44 99 74 24 24 24 24 23 14 -1 74 58 24 20 14 8 -2 -16 -36 107 82 32 32 32 32 31 22 7 84 68 34 30 24 18 8 -6 -26 115 90 40 40 40 40 39 30 15 100 84 50 46 40 34 24 10 -10 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns ck, ck\ differential slew rate ? t is, ? t ih derating (ps) - ac/dc-based, ac150 threshold; v ih (ac) = v ref (dc) + 150mv, v il (ac) = v ref (dc) - 150mv shaded cells indicate slew-rate combinations not supported slew rate (v/ns) t vac at 175mv(ps) t vac at 150mv(ps) >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5 175 170 167 163 162 161 159 155 150 150 t able 54: m inimum r equired t ime t v ac above v ih (ac) for a v alid t ransition 75 57 50 38 34 29 22 13 0 0 below vil(ac)
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 60 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product notes: 1. both the clock and the strobe are drawn on different time scales. v ss setup slew rate risin g signal setup slew rate falling signal ?tf ?tr = = v cc q v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) max v il ( dc ) max nominal slew rate v ref to ac region t vac t vac dqs dqs# ck# ck t is t ih t is t ih nominal slew rate v ref to ac region v ref ( dc ) - v il ( ac ) max ?tf v ih ( ac ) min - v ref ( dc ) ?tr f igure 25 - n ominal s lew r ate and t vac for t is (c ommand and a ddress ? c lock )
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 61 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 26 - n ominal s lew r ate for t ih (c ommand and a ddress ? c lock ) notes: 1. both the clock and the strobe are drawn on different time scales. v ss hol d slew rate falling signal hol d slew rate rising signal ?tr ?tf = = v cc q v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) max v il ( ac ) max nominal slew rate dc to v ref region dqs dqs# ck # ck t is t ih t is t ih dc to v ref region nominal slew rate v ref ( dc ) - v il ( dc ) max ?tr v ih ( dc ) min - v ref ( dc ) ?tf
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 62 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 27 - t angent l ine for t is (c ommand and a ddress ? c lock ) notes: 1. both the clock and the strobe are drawn on different time scales. v ss setup slew rate rising signal setup slew rate falling signal ?tf ?tr = = v cc q v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) max v il ( ac ) max tangent line v ref to ac region nominal line t vac t vac dqs dqs# ck # ck t is t ih t is t ih v ref to ac region tangent line nominal line tangent line (v ih [ dc ] min - v ref [ dc ]) ?tr tangent line (v ref [ dc ] - v il [ ac ] max) ?tf
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 63 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 28 - t angent l ine for t ih (c ommand and a ddress ? c lock ) notes: 1. both the clock and the strobe are drawn on different time scales. v ss hol d slew rate falling signal ?tr = v cc q v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) max v il ( ac ) max tangent line dc to v ref region hol d slew rate rising signal = dqs dqs # ck# ck t is t ih t is t ih dc to v ref region tangent line nominal line nominal line ?tr tangent line (v ref [ dc ] - v il [ dc ] max) ?tr tangent line (v ih [ dc ] min - v ref [ dc ]) ?tf
? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 t able 56: d erating v alue for t ds/ t dh ? ac175/dc100 - b ased dq slew rate v/ns 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns dqs, dqs# differential slew rate ? t ds, ? t dh derating (ps) ? ac175/d100-based shaded cells indicate slew-rate combinations not supported logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 64 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product data setup, hold and derating the total t ds (setup time) and t dh (hold time) required is calculated by adding the data sheet t ds (base) and t dh (base) values (see table 55) to the ? t ds and ? t dh derating values (see table 56), respectively. although the total setup time for slow slew rates might be negative, a valid input signal is still required to complete the tra nsition and to reach v ih /v il (ac). for slew rates which fall between the values listed in table 57, the derating values may be obtained by linear interpolation. setup ( t ds) nominal slew rate for a rising signal is de ned as the slew rate between the last crossing of v ref (dc) and the rst crossing of v ih (ac) min. setup ( t ds) nominal slew rate for a falling signal is de ned as the slew rate between the last crossing of v ref (dc) and the rst crossing of v il (ac) max. if the actual signal is always earlier than the nominal slew rate line between the shaded ?v ref (dc)-to-ac region?, use the nominal slew rate derating value (see figure 29). if the actual signal is later than the nominal slew rate line anywhere between the shaded ?v ref (dc)-to-ac region?, the slew rate of a tangent line to the actual signal from the ac level to the dc level is used for the derating value (see figure 31). hold ( t dh) nominal slew rate for a rising signal is de ned as the slew rate between the last crossing of v il (dc) max and the rst crossing of v ref (dc). hold ( t dh) nominal slew rate for a falling signal is de ned as the slew rate between the last crossing of v ih (dc) min and the rst crossing of v ref (dc). if the actual signal is always later than the nominal slew rate line between the shaded ?dc-to-v ref (dc) region?, use the nominal slew rate for derating value (see figure 30). if the actual signal is earlier than the nominal slew rate line anywhere between the shaded ?dc-to-v ref (dc) region?, the slew rate of a tangent line to the actual signal from the ?dc-to-v ref (dc) region?, is used for the derating value (see figure 32). symbol ddr3-800 ddr3-1066 ddr3-1333 units reference t ds(base)ac175 t ds(base)ac150 t ds(base)dc100 v ih (ac)/v il (ac) v ih (ac)/v il (ac) v ih (ac)/v il (ac) t able 55: d ata s etup and h old v alues at 1v/ ns (dqs x , dqs x \ at 2v/ ns ) ? ac/dc b ased - 30 65 75 125 150 25 75 100 ps ps ps 88 59 0 50 34 0 88 59 0 -2 50 34 0 -4 88 59 0 -2 -6 50 34 0 -4 -10 67 8 6 2 -3 42 8 4 -2 -8 16 14 10 5 -1 16 12 6 0 -10 22 18 13 7 -11 20 14 8 -2 -16 26 21 15 -2 -30 24 18 8 -6 -26 29 23 5 -22 34 24 10 -10
? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 t able 57: d erating v alue for t ds/ t dh ? ac150/dc100 - b ased dq slew rate v/ns 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns dqs, dqs# differential slew rate ? t ds, ? t dh derating (ps) ? ac150/dc100-based shaded cells indicate slew-rate combinations not supported logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 65 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product 75 50 0 50 34 0 75 50 0 0 50 34 0 -4 75 50 0 0 0 50 34 0 -4 -10 58 8 8 8 8 42 8 4 -2 -8 16 16 16 16 15 16 12 6 0 -10 24 24 24 23 14 20 14 8 -2 -16 32 32 31 22 7 24 18 8 -6 -26 40 39 30 15 34 24 10 -10 slew rate (v/ns) t vac at 175mv(ps) [min] t vac at 150mv(ps) [min] >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5 175 170 167 163 162 161 159 155 150 150 t able 58: r equired t ime t vac a bove v ih (ac) (b elow v il [ac]) for a v alid t ransition 75 57 50 38 34 29 22 13 0 0
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 66 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 29 - n ominal s lew r ate and t vac for t ds (dq ? s trobe ) notes: 1. both the clock and the strobe are drawn on different time scales. v ss setup slew rate rising signal setup slew rate ?tf ?tr = = v cc q v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) max v il ( ac ) max nominal slew rate v ref to ac region t vac t vac t dh t ds dqs dqs# t dh t ds ck# ck v ref to ac region nominal slew rate v ih ( ac ) min - v ref ( dc ) ?tr v ref ( dc ) - v il ( ac ) max ?tf rising signal
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 67 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 30 - n ominal s lew r ate for t dh (dq ? s trobe ) notes: 1. both the clock and the strobe are drawn on different time scales. v ss hold slew rate falling signal hold slew rate rising signal ?tr ?tf = = v cc q v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) max v il ( ac ) max nominal slew rate dc to v ref region t dh t ds dqs dqs# t dh t ds ck# ck dc to v ref region nominal slew rate v ref ( dc ) - v il ( dc ) max ?tr v ih ( dc ) min - v ref ( dc ) ?tf
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 68 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 31 - n ominal s lew r ate and t vac for t ds (dq ? s trobe ) notes: 1. both the clock and the strobe are drawn on different time scales. v ss setup slew rate rising signal setup slew rate falling signal ?tf ?tr = = v cc q v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) max v il ( ac ) max tangent line v ref to ac region nominal line t vac t vac t dh t ds dqs dqs# t dh t ds ck# ck v ref to ac region tangent line nominal line ?tr tangent line (v ref [ dc ] - v il [ ac ] max) ?tf tangent line (v ih [ ac ] min - v ref [ dc ])
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 69 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 32 - n ominal s lew r ate for t dh (dq ? s trobe ) notes: 1. both the clock and the strobe are drawn on different time scales. v ss hol d slew rate falling signal ?tf ?tr = v cc q v ih ( ac ) min v ih ( dc ) min v ref ( dc ) v il ( dc ) max v il ( ac ) max tangent line dc to v ref region hol d slew rate = dqs dqs# ck# ck dc to v ref region tangent line nominal line nominal line tangent line (v ih [ dc ] min - v ref [ dc ]) ?tf tangent line (v ref [ dc ] - v il [ dc ] max) ?tr t ds t dh t ds t dh falling signal
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 70 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product p ackage o utline d imensions function symbol cycle cycle cs\ ras\ cas\ we\ ba [2:0] a n a 12 a 10 a [11,0:0] notes mode register set refresh self refresh entry self refresh exit single-bank precharge precharge all banks bank activate no operation device deselected power-down entry power-down exit zq calibration long zq calibration short 6 6,7 8 8 8 8 8 8 8 8 8 8 8 8 9 10 6 6,11 12 t able 59: t ruth t able - c ommand l l l l l l l l l l l l l l l l l l l h l l l l l l l l h h h h h h h h h h h h h x h h l l l l l l h h h h h h h h h h h h h x h h l h h l l h l l l l l l h h h h h h h x l l ba v v v vba v ba ba ba ba ba ba ba ba ba ba ba ba ba v x v v x x v v v v v rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu v x v v x x v v v v v v l h v l h v l h v l h v x v v x x v v v l h l l l h h h l l l h h h v x v v h l v v v v v ca ca ca ca ca ca ca ca ca ca ca ca ca v x v v x x mrs ref sre srx pre prea act wr wrs4 wrs8 wrap wraps4 wraps8 rd rds4 rds8 rdap rdaps4 rdaps8 nop des pde pdx zqcl zqcs h h h l h h h h h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h h h h h l h h h write write with auto precharge read read with auto precharge bl8mrs bc4mrs bc4otf bl8otf bl8mrs bc4mrs bc4otf bl8otf bl8mrs bc4mrs bc4otf bl8otf bl8mrs bc4mrs bc4otf bl8otf h l l h l h v h v h v h h v h v h v h v h v h v cke prev next burst reads or writes cannot be terminated or interrupted, mrs 8. ( xed) and otf bl/bc are de ned in mr0. the purpose of the nop command is to prevent the sdram from reg- 9. istering any unwanted commands. a nop will not terminate and opera- tion that is in execution. the des and nop commands perform similarly. 10. the power-down mode does not perform any refresh opera- 11. tions. zq calibration long is used for either zqint ( rst zqcl com- 12. mand during initialization) or zqoper (zqcl command after initializa- tion). notes: commands are de ned by states of cs\, ras\, cas\, we\, and cke at 1. the rising edge of the clock. the msb of ba, ra, and ca are device- density and con guration-dependent. reset\ is low enabled and used only for asynchronous reset. thus, 2. reset\ must be held high during any normal operation. the state of odt does not affect the states described in this table. 3. operations apply to the bank de ned by the bank address. for mrs, ba 4. selects one of four mode registers. ?v? means ?h? or ?l? (a de ned logic level), and ?x? means ?don?t care?. 5. see table 59 for additional information on cke transition. 6. self refresh exit is asynchronous. 7. commands truth table
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 71 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product current state 3 power-down self refresh bank(s) active reading writing precharging refreshing all banks idle t able 60: t ruth t able - cke l h l h l l l l l l (n-1) previous cycle 4 (n) present cycle 4 (ras\, cas\, we\, cs\) command 5 action 5 notes l l l h h h h h h h ?don?t care? des or nop ?don?t care? des or nop des or nop des or nop des or nop des or nop des or nop refresh maintain power-down power-down exit maintain self refresh self refresh exit active power-down entry power-down entry power-down entry precharge power-down entry precharge power-down entry self refresh 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2,6 cke cke (n) is the logic state of cke at clock edge n, cke (n-1) was the 4. state of cke at the previous clock edge. command is the command registered at the clock edge (must be a 5. legal command as de ned in table 58). action is a result of com- mand. odt does not affect the states described in this table and is not listed. idle state = all banks are closed, no data bursts are in progress, cke is 6. high and all timings from previous operations are satis ed. all self refresh exit and power-down exit parameters are also satis- ed. notes: all states and sequences not shown are illegal or reserved unless explic- 1. itly described elsewhere in this document. t 2. cke(min) means cke must be registered at multiple consecutive posi- tive clock edges. cke must remain at the valid input level the entire time it takes to achieve the required number of registration clocks. thus, after any cke transition, cke may not transition from its valid level during the time period of t is + t cke(min) + t ih. current state = the state of the sdram immediately prior to clock edge 3. n. deselect (des) the des command (cs\ high) prevents new commands from being exe- cuted by the sdram. operations already in progress are not affected. no operation (nop) the nop command (cs\ low) prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. zq calibration zq calibration long (zqcl) the zqcl command is used to perform the initial calibration during a power-up initialization and reset sequence. this command may be issued at any time by the controller depending on the system environment. the zqcl command triggers the calibration engine inside the sdram. after calibration is achieved, the calibrated values are transferred from the calibration engine to the sdram i/o, which are re ected as updated r on and odt values. the sdram is allowed a timing window de ned by either t zqinit or t zqoper to perform the full calibration and transfer of values. when zqcl is issued during the initialization sequence, the timing parameter tzqinit must be satis ed. when initialization is complete, subsequent zqcl commands require the timing parameter t zqoper to be satis ed. zq calibration short (zqcs) the zqcs command is used to perform periodic calibrations to account for small voltage and temperature variations. the shorter timing window is provided to perform the reduced calibration and transfer of values as de ned by timing parameter t zqcs. a zqcs command can effectively correct a minimum of 0.5% r on and r tt impedance errors within 64 clock cycles, assuming the maximum sensitivities speci ed in table 40 and table 41.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 72 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product activate the activate command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba [2:0] inputs selects the bank, and the address provided on inputs a[n:0] selects the row. this row remains open (or active) for accesses until a pre- charge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the address provided on inputs a[2:0] selects the starting column address depending on the burst length and burst type selected (see table 65). the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be pre- charged at the end of the read burst. if auto precharge is not selected, the row will remain open for subsequent accesses. the value on input a12 (if enabled in the mode register) when the read command is issued, determines whether bc4 (chop) or bl8 is used. after a read command is issued, the read burst may not be interrupted. a summary of read commands is shown in table 61. t able 61: r ead c ommand s ummary function symbol cycle cycle cs\ ras\ cas\ we\ ba [2:0] a n a 12 a 10 a [11,0:0] notes l l l l l l h h h h h h l l l l l l h h h h h h ba ba ba ba ba ba rfu rfu rfu rfu rfu rfu v l h v l h l l l h h h ca ca ca ca ca ca rd rds4 rds8 rdap rdaps4 rdaps8 h h h h h h cke prev next read read with auto precharge bl8mrs bc4mrs bc4otf bl8otf bl8mrs bc4mrs bc4otf bl8otf write the write command is used to initiate a burst write access to an active row. the value on the ba[2:0] inputs selects the bank. the value on input a10 determines whether or not auto precharge is used. the value on input a12 (if enabled in the mode register [mr]) when the write command is issued, determines whether bc4 (chop) or bl8 is used. the write command summary is shown in table 62. t able 62: w rite c ommand s ummary function symbol cycle cycle cs\ ras\ cas\ we\ ba [2:0] a n a 12 a 10 a [11,0:0] notes l l l l l l h h h h h h l l l l l l l l l l l l ba ba ba ba ba ba rfu rfu rfu rfu rfu rfu v l h v l h l l l h h h ca ca ca ca ca ca wr wrs4 wrs8 wrap wraps4 wraps8 h h h h h h cke prev next write write with auto precharge bl8mrs bc4mrs bc4otf bl8otf bl8mrs bc4mrs bc4otf bl8otf
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 73 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product the precharge command is used to deactivate the open row in a particular bank or in all banks. the bank(s) are available for a subsequent row access at a speci ed time ( t rp) after the precharge command is issued, except in the case of concurrent auto precharge. a read or write command to a different bank is allowed during concurrent auto precharge as long as it does not interrupt the data transfer in the cur- rent bank and does not violate any other timing parameters. input a10 determines whether one or all banks are precharged. in the case where only one bank is recharged. inputs ba[2:0] select the bank; otherwise, ba[2:0] are treated as ?don?t care?. after a bank is precharged, it is in the idle state and must be activated prior to any read or write com- mands being issued to that bank. a precharge command is treated as a nop if there is no open row in that bank (idle state) or if the previ- ously open row is already in the process of precharging. however, the precharge period is determined by the last precharge command issued to the bank. precharge refresh is used during normal operation of the sdram and is analogous to cas\-before ras\ (cbr) refresh or auto refresh. this command is non-persistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh command. the sdram requires refresh cycles at an average interval of 7.8 s (maximum when tc 85 ? c or 3.9 s max when tc 95 ? c). the refresh period begins when the refresh command is registered and ends t rfc (min) later. to allow for improved ef ciency in scheduling and switching between tasks, some exibility in the absolute refresh interval is provided. a maximum of eight refresh commands can be posted to any given sdram, mean- ing that the maximum absolute interval between any refresh command and the next refresh command is nine times the maximum average interval refresh rate. self refresh may be entered with up to eight refresh commands being posted. after exiting self refresh (when entered with posted refresh commands) additional posting of refresh commands is allowed to the extent the maximum number of cumulative posted refresh commands (both pre and post self refresh) does not exceed eight refresh commands. refresh f igure 33 - r efresh m ode notes: 1. nop commands are shown for ease of illustration; other valid commands may be possible at these times. cke must be active during the precharge, activate, and refresh commands, but may be inactive at other times (see power-down mode on page 153). nop 1 nop 1 nop 1 pre ra bank(s) 3 ba ref nop 1 ref 2 nop 1 act nop 1 one bank all banks t ck t ch t cl ra t rfc 2 t rp t rfc (min) t0 t1 t2 t3 t4 ta0 tb0 ta1 tb1 tb2 dont care indicates a break in time scale valid 1 valid 1 valid 1 ck ck# command cke address a10 ba[2:0] dq 4 dm 4 dqs, dqs# 4
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 74 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product the self refresh command is used to retain data in the sdram, even if the rest of the system is powered down. when in the self refresh mode, the sdram retains data without external clocking. the self refresh mode is also a convenient method used to enable/disable the dll as well as to change the clock frequency within the allowed synchronous operating range. all power supply inputs (including v refca and v refdq ) must be maintained at valid levels upon entry/exit and during self refresh mode operation. all power supply inputs (including v refca and v refdq ) must be maintained at valid levels upon entry/exit and during self refresh mode under certain conditions: ? vss< v refdq < vcc is maintained ? v refdq is valid and stable prior to cke going back high ? the rst write operation may not occur earlier than 512 clocks after v refdq is valid ? all other self refresh mode exit time requirements are met. self refresh if the dll is disabled by the mode register (mr1[0] can be switched during initialization or later), the sdram is targeted, but not guaranteed to operate similarly to the normal mode with a few notable exceptions: the sdram supports only one value of cas latency (cl=6) and one value of cas write latency (cwl=6). ? dll disable mode affects the read data clock-to-data strobe relationship ( ? t dqsck), but not the read data-to-data strobe relationship ( t dqsq, t qh). special attention is needed to line the read data up with the controller time domain when the dll is disabled. in normal operation (dll on), ? t dqsck starts from the rising clock edge al + cl cycles after the read command. in dll disable mode, t dqsck starts al = cl ? 1 cycles after the read command. additionally, with the dll disabled, the value of t dqsck could be larger than t ck. the odt feature is not supported during dll disable mode (including dynamic odt). the odt resistors must be disabled by contin uously registering the odt ball low by programming r tt _norm mr1[9,6,2] and r tt _wr mr2[10,9] to ?0? while in dll disable mode. speci c steps must be followed to switch between the dll enable and dll disable modes due to a gap in the allowed clock rates between the two modes ( t ck[avg]max and t ck[dll disable] min, respectively). the only time the clock is allowed to cross this clock rate gap is during self refresh mod e. thus, the required procedure for switching from the dll enable to dll disable mode is to change frequency curing self refresh (see figure 34): starting from the idle state (all banks are precharged, all timings are ful lled, odt is turned off, and r 1. tt _nom and r tt _wr are high-z), set mr1[0] to ?1? to disable the dll. enter self refresh mode after 2. t mod has been satis ed. after 3. t cksre is satis ed, change the frequency to the desired clock rate. self refresh may be exited when the clock is stabled with the new frequency for 4. t cksrx. the sdram will be ready for its next command in the dll disable mode after the greater of 5. t mrd or t mod has been satis ed. a zqcl command should be issued with appropriate timing met as well. dll disable mode
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 75 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 34 - dll e nable m ode to dll d isable m ode command t0 t1 ta0 ta1 tb 0 tc0 7 6 td 0 td 1 te0 te1 tf0 ck ck# odt 9 vali d 1 don t care vali d 1 sre 3 nop mrs 2 nop srx 4 mrs 5 vali d 1 nop nop indicates a break in time scale t mod t cksre t mod t xs t ckesr cke t cksrx 8 notes: any valid command. 1. disable dll by setting mr1[0] to ?1.? 2. wait 3. t xs, then set mr1[0] to ?0? to enable dll. wait 4. t mrd, then set mr0[8] to ?1? to begin dll reset. wait 5. t mrd, update registers (cl, cwl, and write recovery may be necessary). wait 6. t mod, any valid command. starting with the idle state. 7. change frequency. 8. clock must be stable at least 9. t cksrx. static low in case r 10. tt _nom or r tt _wr is enabled; otherwise, static low or high. a similar procedure is required for switching from the dll disable mode back to the dll enable mode. this also requires changin g the frequency during self refresh mode (see figure 44 on page 100). 1. starting from the idle state (all banks are precharged, all timings are ful lled, odt is turned off, and r tt _nom and r tt _wr are high-z), enter self refresh mode. 2. after t cksre is satis ed, change the frequency to the new clock rate. 3. self refresh may be exited when the clock is stable with the new frequency for t cksrx. after t xs is satis ed, update the mode registers with the appropriate values. at a minimum, set mr1[0] to ?0? to enable the dll. wait t mrd, then set mr0[8] to ?1? to enable dll reset. 4. after another t mrd delay is satis ed, then update the remaining mode registers with the appropriate values. 5. the dram will be ready for its next command in the dll enable mode after the greater of t mrd or t mod has been satis ed. however, before applying any command or function requiring a locked dll, a delay of t dllk after dll reset must be satis ed. a zqcl command should be issued with the appropriate timings met as well.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 76 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 35- dll d isable m ode to dll e nable m ode indicates a break in time scale t c t dllk cke t0 t a 0t a 1tb0 t c 0t c 1td0t e 0 tf0 t g 0 ck ck# odt 10 sre 1 nop command nop srx 2 mrs 3 mrs 4 mrs 5 vali d 6 vali d don t care 8 7 t ck sr e th0 t cksrx 9 odtl off + 1 t ck t xs t mrd t mrd kesr notes: enter self refresh. 1. exit self refresh. 2. wait 3. t xs, then set mr1[0] to ?0? to enable dll. wait 4. t mrd, then set mr0[8] to ?1? to begin dll reset. wait 5. t mrd, update registers (cl, cwl, and write recovery may be necessary). wait 6. t mod, any valid command. starting with the idle state. 7. change frequency. 8. clock must be stable at least 9. t cksrx. static low in case r 10. tt _nom or r tt _wr is enabled; otherwise, static low or high. the clock frequency range for the dll disable mode is speci ed by the parameter t ckdll_dis. due to latency counter and timing restrictions, only cl = 6 and cwl = 6 are supported. dll disable mode will affect the read data clock to data strobe relationship ( t dqsck) but not the data strobe to data relationship ( t dqsq, t qh). special atten- tion is needed to the controller time domain. compared to the dll on mode where t dqsck starts from the rising clock edge al + cl cycles after the read command, the dll disable mode t dqsck starts al + cl - 1 cycles after the read command (see figure 45 on page 101). write operations function similarly between the dll enable and dll disable modes; however, odt functionality is not allowed wit h dll disable mode.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 77 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 36 - dll d isable t dqsck t iming t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 don t care transitioning data vali d nop read nop nop nop nop nop nop nop nop nop ck ck # command add ress di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 dq bl8 dll on dqs, dqs# dll on dq bl8 dll disable dqs, dqs# dll off dq bl8 dll disable dqs, dqs# dll off rl = al + c l = 6 (c l = 6, al = 0) c l = 6 di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 t dqsck ( dll _ dis ) min t dqsck ( dll _ dis ) max rl (dll disable) = al + (c l - 1) = 5 when the ddr3 sdram is initialized, it requires the clock to be stable during most normal states of operation. this means that after the clock frequency has been set to the stable state, the clock period is not allowed to deviate except what is allowed for by the clock jitter and spread spectrum clocking (ssc) speci cations. the input clock frequency can be changed from one stable clock rate to another under two conditions: self refresh mode and prec harge power-down mode. outside of these two modes, it is illegal to change the clock frequency. for the self refresh mode condition, when the ddr3 sdram has been successfully placed into self refresh mode and t cksre has been satis ed, the state of the clock becomes a ?don?t care?. when the clock becomes a ?don?t care?, changing the clock frequency is permissible, provided the new clock frequency is stable prior to t cksrx. when entering and exiting self refresh mode for the sole purpose of changing the clock frequency, the self refresh entry and exit speci cations must still be met. the precharge power-down mode condition is when the ddr3 sdram is in precharge power-down mode (either fast exit mode or slow e xit mode). either odt must be at a logic low or r tt _nom and r tt _wr must be disabled via mr1 and mr2. this ensures r tt _nom and r tt _wr are in an off state prior to entering precharge power-down mode while maintaining cke at a logic low. a minimum of t cksre must occur after cke goes low before the clock frequency can change. the ddr3 sdram input clock frequency is allowed to change only within the minimum and maximum oper ating frequency speci- ed for the particular speed/temperature grade ( t ck [avg] min to t ck [avg] max) device. during the input clock frequency change, cke must be held at a stable low level. when the input clock frequency is changed, a stable clock must be provided to the sdram, t cksrx before precharge power-down may be exited. after precharge power-down is exited and t xp has been satis ed, the dll must be reset via the mrs. depending on the new clock frequency, additional mrs commands may need to be issued. during the dll lock time, r tt _nom and r tt _wr must remain in an off state. after the dll lock time, the sdram is ready to operate with a new clock frequency (period). this process is depicted in figure 37. input clock frequency change
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 78 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 37- c hange f requency d uring p recharge p ower -d own ck ck# command nop nop nop address cke dq dm dqs, dqs# nop t ck enter precharge power-down mode exit precharge power-down mode t0 t1 ta0 tc0 tb0 t2 dont care t cke t xp mrs dll reset valid valid nop t ch t ih t is t cl tc1 td0 te1 td1 t cksre t ch b t cl b t ck b t ch b t cl b t ck b t ch b t cl b t ck b t cpded odt nop te0 previous clock frequency new clock fre quency frequency change indicates a break in time scale t ih t is t ih t is t dllk t aofpd/ t aof t cksrx high-z high-z notes: applicable for both slow-exit and fast-exit precharge power-down modes. 1. t 2. aofpd and t aof must be satis ed and outputs high-z prior to t1 (see ?on-die termination (odt)? on page 161 for exact requirements). if the r 3. tt _nom feature was enabled in the mode register prior to entering precharge power-down mode, the odt signal must be continuously registered low ensuring r tt is in an off state. if the r tt _nom feature was disabled in the mode register prior to entering precharge power-down mode, r tt will remain in the off state. the odt signal can be registered either low or high in this case.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 79 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product for better signal integrity, ddr3 sdram memory sub-system designs have adopted use of y-by topology for the commands, addresses, control signals and clocks. write leveling is a scheme for the memory controller to de-skew the dqsx strobe (dqsx, dqsx\) to ck relationship at th e sdram with a simple feedback feature provided it by the ddr3 sdram itself. write leveling is generally used as part of the initialization process, if required. for normal sdram operation, this feature must be disabled. this is the only sdram operation where the dqs functions as an input (to captu re the incoming clock) and the dqs function as outputs (to report the stat of the clock). note that nonstandard odt schemes are required. the memory controller using the write leveling procedure must have adjustable delay setting on its dqs strobe to align the risi ng edge of dqs to the clock at the sdram pins. this is accomplished when the sdram asynchronously feeds back the ck status via the dq bus and samples with the rising edge of dqs. the controller repeatedly delays the dqs strobe until a ck transition from ?0? to ?1? is detected. the dqs delay establi shed through this procedure helps ensure t dqss, t dss, and t dsh speci cations in systems that use y by topology by de-skewing the trace length mismatch. a conceptual timing of this procedure is shown in figure 38. write leveling f igure 38- w rite l eveling c oncept ck ck# source differential dqs differential dqs differential dqs dq dq ck ck# destination destination push dqs to capture 0C1 transition t0 t1 t2 t3 t4 t5 t6 t7 t0 t1 t2 t3 t4 t5 t6 tn ck ck# t0 t1 t2 t3 t4 t5 t6 tn dont care 1 1 0 0
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 80 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product when write leveling is enabled, the rising edge of dqs samples ck and the rime dq outputs the sampled ck?s status. the prime d q for each of the (4) words contained in the imod is dq0 for the low byte, dq8 for the high byte. it outputs the status of ck sampled by ldqsx a nd udqsx. all other dqs (dq[7:1], dq[15:9] for the low word, dq[23:17],dq[31:25] for the next word, dq[39:33], dq[47:41] for the next and dq[55:49], dq [63:57] for the high word dq[71:64] for the ecc byte) continue to drive low. two prime dq on each of the (4) words contained in the ldi imod allow each byte lane to be leveled independently. write leveling a memory controller initiates the sdram write leveling mode by setting the mr1[7] to a ?1?, assuming the other programmable fea tures (mr0, mr1, mr2, and mr3) are rst set and the dll is fully reset and locked. the dq balls enter the write leveling mode going from a ?high-z? state to an un de ned driv- ing state so the dq bus should not be driven. during write leveling mode, only the nop and des commands are allowed. the memo ry controller should attempt to level only one rank at a time; thus, the outputs of other ranks should be disabled by setting mr1[12] to a ?1?. the memory controller may assert odt after a t mod delay as the sdram will be ready to process the odtl on delay (wl-2 t ck), provided it does not violate the aforementioned t mod delay requirement. the memory controller may drive ldqsx, udqsx low and ldqsx\, udqsx\ high after t wldqsen has been satis ed. the controller may begin to toggle ldqsx, udqsx after t wlmrd (one l[u]dqss toggle is dqss transitioning from a low state to a high state with l[u]dqsx\ transitioning from a high stat e to a low state, then both transition back to their original states). at a minimum, odtl on and t aon must be satis ed at least one clock prior to dqs tog- gling. after t wlmrd and dqs low preamble ( t wpre) have been satis ed, the memory controller may provide either a single dqsx toggle or multiple dqsx toggles to sample ck for a given dqsx to ck skew. each dqs toggle must not violate t dqsl (min) and t dqsh (min) speci cations. t dqsl (max) and t dqsh (max) speci cations are not applicable during write leveling mode. the dqsx must be able to distinguish the ck?s rising edge within t wls and t wlh. the prime dq will output the ck?s status asynchronously from the associated dqsx rising edge ck capture within t wlo. the remaining dqs that always drive low when dqs is toggling must be low within t wloe after the rst t wlo is satis ed (the prime dqs going low). as previously noted, dqsx is an input and not an output during this process. figure 39 depicts the basic timing parameters for the overall write leveling procedure. the memory controller will likely sample each applicable prime dq state and determine whether to increment or decrement it dqs delay setting. after the memory controller performs enough dqsx toggles to detect the ck?s ?0-1? transition, the memory controller should lock the dqs d elay setting for the sdram imod device. after locking the dqs setting, leveling for the rank will have been achieved, and the write leveling mode for the rank should be disabled or reprogrammed (if write leveling of another rank follows). write leveling procedure
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 81 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 39- w rite l eveling s equence ck ck# command t1 t2 early remaining dq late remaining dq t wloe nop 2 nop mrs 1 nop nop t wls t wlh dont care undefined driving mode indicates a break in time scale prime dq 5 differential dqs 4 odt t mod t dqsl 3 t dqs h 3 t dqsh 3 t wlo t wlmrd t wldqsen t wlo t wlo t wlo t dqsl 3 nop nop nop nop nop nop nop notes: mrs: load mr1 to enter write leveling mode. 1. nop: nop or des. 2. dqs, dqs# needs to ful ll minimum pulse width requirements 3. t dqsh (min) and t dqsl (min) as de ned for regular writes. the maximum pulse width is system-dependent. differential dqs is the differential data strobe (dqs, dqs#). timing reference points are the zero 4. crossings. the solid line represents dqs; the dotted line represents dqs#. dram drives leveling feedback on a prime dq (dq0 for x4 and x8). the remaining dq are driven 5. low and remain in this state throughout the leveling procedure. after the ddr3 sdram imod has been write leveled, the controller must exit from write leveling mode before the normal mode can be used. figure 40 depicts a general procedure in exiting write leveling. after the last rising dqs (capturing a ?1? at t0), the memory contro ller should stop driving the dqs signals after t wlo (max) delay plus enough delay to enable the memory controller to capture the applicable prime dq state (at ? tb0). the dq balls become unde ned when dqs no longer remains low and they remain unde ned until t mod after the mrs command (at te1). the odt input should be deasserted low such that odtl off (min) expires after the dqsx is no longer driving low. when odt low satis es t is, odt must be kept low (at ?tb0) until the sdram is ready for either another rank to be leveled or until the normal mode can be used. after dqs termination is switched off, write level mode should be disabled via the mrs command (at tc2). after t mod is satis ed (at te1), any valid command may be registered by the sdram. some mrs commands may be issued after t mrd (at td1). write leveling exit mode
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 82 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 40- e xit w rite l eveling notes: 1. the dq result, = 1, between ta0 and tc0, is a result of the dqs, dqs# signals capturing ck high just after the t0 state. nop ck t0 t1 t2 ta0 tb0 tc0 tc1 tc2 td0 td1 te0 te1 ck# command odt r tt _dq nop r m p o n p o n p o n p o n p o n s nop nop add ress mr1 valid valid valid valid don t care transitioning r tt dqs, r tt dqs r # tt _ nom undefined driving mode t aof (max) t mrd indicates a break in time scale dqs , dqs# ck = 1 dq t is t aof (min) t mod t wlo + t wloe odtl off
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 83 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product initialization the following sequence is required for power up and initialization, as shown in figure 41. apply power. reset\ is recommended to be below 0.2 x vccq during power ramp to ensure the outputs remain disabled (high-z) and 1. odt off (r tt is also high-z). all other inputs, including odt may be unde ned. during power up, either of the following conditions may exist and must be met: condition a: ? vcc and vccq are driven from a single power source and are ramped with a maximum delta voltage between them of ? v 300mv. ? slope reversal of any power supply signal is allowed. the voltage levels on all balls other than vcc, vccq, vss and vssq must be less than or equal to vccq and vcc on one side and must be greater than or equal to vssq and vss on the other side. both vcc and vccq power supplies ramp to vcc (min) and vccq (min) within ? t vccpr=200ms. both vcc and vccq power supplies ramp to vcc (min) and vccq (min) within ? t vccpr=200ms. v ? refdq tracks vcc x 0.5, v refca tracks vcc x 0.5. v ? tt is limited to 0.95v when the power ramp is complete and is not applied directly to the device; however, t vtd should be greater than or equal to zero to avoid device latchup. ? condition b: vcc may be applied before or at the same time as vccq. ? vccq may be applied before or at the same time as v ? tt , v refdq and v refca . no slope reversals are allowed in the power supply ramp for this condition. ? until stable power, maintain reset\ low to ensure the outputs remain disabled (high-z). after the power is stable, reset\ must be 2. low for at least 200 s to begin the initialization process. odt will remain in the high-z state while reset\ is low and until cke is registered high. cke must be low 10ns prior to reset\ transitioning high. 3. after reset\ transitions high, wait 500 s (minus one clock) with cke low. 4. after this cke low time, cke may be brought high (synchronously) and only nop or des commands may be issued. the clock must be 5. present and valid for at least 10ns (and a minimum of ve clocks) and odt must be driven low at least tis prior to cke being registered high. when cke is registered high, it must be continuously registered high until the full initialization process is complete. after cke is registered high and after 6. t xpr has been satis ed, mrs commands may be issued. issue an mrs (load mode) command to mr2 with the applicable settings (provide low to ba2 and ba0 and high to ba1). issue an mrs command to mr3 with the applicable settings. 7. issue an mrs command to mr1 with the applicable settings, including enabling the dll and con guring odt. 8. issue and mrs command to mr0 with the applicable settings, including a dll reset command. 9. t dllk (512) cycles of clock input are required to lock the dll. issue a zqcl command to calibrate r 10. tt and ron values for the process voltage temperature (pvt). prior to normal operation. t zqinit must be satis ed. when 11. t dllk and t zqinit have been satis ed, the ddr3 sdram will be ready for normal operation. operations
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 84 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 41- i nitialization s equence ck e r tt ba[2:0] all voltage supplies valid and stable t = 200s (min) dm dqs add ress a10 ck ck# t cl command nop t0 ta0 don t care t cl t is t ck odt dq tb 0 t dllk mr1 with dll ena ble mr0 with dll reset t mrd t mod mrs mrs ba0 = h ba1 = l ba2 = l ba0 = l ba1 = l ba2 = l code code code code valid valid valid valid normal operation mr2 mr3 t mrd t mrd mrs mrs ba0 = l ba1 = h ba2 = l ba0 = h ba1 = h ba2 = l code code code code tc0 td 0 v tt v ref v cc q v cc reset# t = 500s (min) t ck s r x sta ble and vali d clo ck valid power-up ramp t (max) = 200ms dram ready for external commands t1 t zq init zq cali bration a10 = h zqcl t is see power-up c onditions in the initialization sequence text, set up 1 t xpr valid = 20ns t io z indicates a break in time scale t (min) = 10ns t vtd
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 85 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product mode registers (mr0-mr3) are used to de ne various modes of programmable operation of the ddr3 sdram imod. a mode register is programmed via the mode register set (mrs) command during initialization and it retains the stored information (except for mr0[8] which is sel f-clearing) until it is either reprogrammed, reset\ goes low, or until the device loses power. contents of a mode register can be altered by re-executing the mrs command. if the user chooses to modify only a subset of the mode register?s variables, all variables must be programmed when the mrs command is issued. reprogramming the mode register will not alter the contents o f the memory array, provided it is performed correctly. the mrs command can only be issued (or re-issued) when all banks are idle and in the precharged state ( t rp is satis ed and no data bursts are in prog- ress). after an mrs command has been issued, two parameters must be satis ed: t mrd and t mod. the controller must wait t mrd before initiating any subsequent mrs commands (see figure 42). mode registers f igure 42- mrs- to -mrs c ommand t iming ( t mrd) valid valid mrs 1 mrs 2 nop nop nop nop t0 t1 t2 ta0 ta1 ta2 ck# ck command add ress cke 3 don t care indicates a break in time scale t mrd notes: prior to issuing the mrs command, all banks must be idle and precharged, 1. t rp (min) must be satis ed, and no data bursts can be in progress.the leveling procedure. t 2. mrd speci es the mrs-to-mrs command minimum cycle time. cke must be registered high from the mrs command until 3. t mrspden (min) (see ?power-down mode? on page 153). for a cas latency change, 4. t xpdll timing must be met before any nonmrs command. the controller must also wait t mod before initiating any nonmrs commands (excluding nop and des), as shown in figure 52 on page 111. the dram requires t mod in order to update the requested features, with the exception of dll reset, which requires additional time. until t mod has been satis ed, the updated features are to be assumed unavailable.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 86 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 43- mrs- to - non mrs c ommand t iming ( t mod) ck ck# command t1 t2 early remaining dq late remaining dq t wloe nop 2 nop mrs 1 nop nop t wls t wlh dont care undefined driving mode indicates a break in time scale prime dq 5 differential dqs 4 odt t mod t dqsl 3 t dqs h 3 t dqsh 3 t wlo t wlmrd t wldqsen t wlo t wlo t wlo t dqsl 3 nop nop nop nop nop nop nop notes: prior to issuing the mrs command, all banks must be idle (they must be precharged, 1. t rp must be satis ed, and no data bursts can be in progress). prior to ta2 when 2. t mod (min) is being satis ed, no commands (except nop/des) may be issued. if rtt was previously enabled, odt must be registered low at t0 so that odtl is satis ed prior 3. to ta1. odt must also be registered low at each rising ck edge from t0 until t mod (min) is satis ed at ta2. cke must be registered high from the mrs command until 4. t mrspden (min), at which time power-down may occur (see ?power-down mode? on page 133). mode register 0 (mr0) the base register, mr0 is used to de ne various ddr3 imod modes of operation. these de nitions include the selection of a burst length, burst type, cas latency, operating mode, dll reset, write recovery and precharge power-down mode, as shown in figure 44.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 87 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product mode register 0 (mr0) accesses within a given burst may be programmed to either a sequential or an interleaved order. the burst type is selected via mr0[3], as shown in figure 44. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 65. ddr3 only supports 4-bit burst chop and 8-bit burst access modes. full interleaved address ordering is supported for reads, while writes are restricted to nibble (bc4) or word (bl8) boundaries. burst type burst length burst length is de ned by mr0[1:0] (see figure 44). read and write accesses to the ddr3 sdram imod are burst-oriented, with the burst length being programmable to ?4? (chop mode). ?8? ( xed burst), or select- able using a12 during a read/write command (on the y). the burst length determines the maximum number of column locations that can be accessed for a given read or write command. when mr0[1:0] is set to ?01? during a read/write command, if a12=0, then bc4 (chop) mode is selected. if a12=1, then bl8 mode is selected. speci c timing diagrams, and turnaround between read/write are shown in the read/write sections of this document. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a[i:2] when the burst length is set to ?4? and by a[i:3] when the burst length is set to ?8? (where ai is the most signi cant column address bit for a given starting loca- tion within the block. the programmed burst length applies to both read and write bursts. f igure 44- m ode r egister 0 (mr0) d efinitions notes: 1. mr0[16, 13, 7, 2] are reserved for future use and must be programmed to 0. 0 1 bl cas# latency bt pd a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register 0 (mr0) address bus 9765432 810 a10 a12 a11 1 a b0 a b 3 12 11 10 1 m3 0 1 read burst type sequential (nibble) interleaved cas latency reserved 5 6 7 8 9 10 11 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 15 dll write recovery reserved 5 6 7 8 10 12 reserved wr 0 0 m12 0 1 precharge pd dll off (slow exit) dll on (fast exit) ba2 16 0 1 burst length fixed bl8 4 or 8 (on-the-fly via a12) fixed bc4 (chop) reserved m0 0 1 0 1 m1 0 0 1 1 m9 0 1 0 1 0 1 0 1 m10 0 0 1 1 0 0 1 1 m11 0 0 0 0 1 1 1 1 m14 0 1 0 1 m15 0 0 1 1 mode register mode register 0 (mr0) mode register 1 (mr1) mode register 2 (mr2) mode register 3 (mr3) a13 14 0 1 0 1 m8 0 1 dll reset no yes
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 88 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product burst length read/write address (a[2,1,0]) type = sequential type = interleaved 4 chop 8 0,1,2,3,z,z,z,z 1,0,3,2,z,z,z,z 2,3,0,1,z,z,z,z 3,2,1,0,z,z,z,z 4,5,6,7,z,z,z,z 5,4,7,6,z,z,z,z 6,7,4,5,z,z,z,z 7,6,5,4,z,z,z,z 0,1,2,3,x,x,x,x 4,5,6,7,x,x,x,x 0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0 0,1,2,3,4,5,6,7 t able 65: b urst o rder notes 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,3,4 1,3,4 1 1 1 1 1 1 1 1 1,3 burst type (decimal) 0,1,2,3,z,z,z,z 1,2,3,0,z,z,z,z 2,3,0,1,z,z,z,z 3,0,1,2,z,z,z,z 4,5,6,7,z,z,z,z 5,6,7,4,z,z,z,z 6,7,4,5,z,z,z,z 7,4,5,6,z,z,z,z 0,1,2,3,x,x,x,x 4,5,6,7,x,x,x,x 0,1,2,3,4,5,6,7 1,2.3,0,5,6,7,4 2,3,0,1,6,7,4,5 3,0,1,2,7,4,5,6 4,5,6,7,0,1,2,3 5,6,7,4,1,2,3,0 6,7,4,5,2,3,0,1 7,4,5,6,3,0,1,2 0,1,2,3,4,5,6,7 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 v v 1 v v 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 v v v read write read write starting column z = data and strobe output drivers in tri-state. 2. x=?don?t care? 3. notes: internal read and write operations start at the same point in time for 1. bc4 as they do for bl8. dll reset is de ned by mr0[8] (see figure 44). programming mr0[8] to ?1? activates the dll reset function. mr0[8] is self-clearing, mean- ing it returns to a value of ?0? after the dll reset function has been initiated. anytime the dll reset function has been initiated, cke must be high and the clock held stable for 512 ( t dllk) clock cycles before a read command can be issued. this is to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in invalid output timing speci cations such as t dqsck timings. dll reset write recovery time is de ned by mr0[11:9] (see figure 44). write recovery values of 5,6,7,8,10 or 12 may be used by programming mr0[11:9]. the user is required to program the correct value of write recovery and is calculated by dividing t wr (ns) by t ck (ns) and round- ing up a non-integer value to the next integer: wr (cycles)=roundup ( t wr[ns]/ t ck [ns]). write recovery
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 89 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product the precharge pd bit applies only when precharge power-down mode is being used. when mr0[12] is set to ?0?, the dll is off during precharge power-down providing a lower standby current mode; how- ever, t xpdll must be satis ed when exiting. when mr0[12] is set to ?1?, the dll continues to run during precharge power-down mode to enable a faster exit of precharge power-down mode; however, t xp must be satis ed when exiting (see power-down mode on page 133). precharge power-down (precharge pd) the cl is de ned by mr0[6:4], as shown in figure 44. cas latency is the delay, as measured in clock cycles, between the internal read command and the availability of the rst bit of valid output data. the cl can be set to 5,6, 8, or 10. ddr3 sdram imods do not support half-clock latencies. examples of cl=6 and cl=8 are shown in figure 45 (below). if an internal read command is registered at clock edge n, and the cas latency is m clocks, the data will be available nominally coincident with clock edge n+m. table 49 indicates the cls supported at available operating frequencies. cas latency (cl) f igure 45- read l atency read nop nop nop nop nop nop nop ck ck# command dq dqs, dqs# dqs, dqs# t0 t1 t2 t3 t4 t5 t6 t7 t8 dont care ck ck# command dq read nop nop nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 di n + 3 di n+ 1 di n + 2 di n + 4 di n di n nop nop al = 0, cl = 8 al = 0, cl = 6 transitioning data notes: for illustration purposes, only cl = 6 and cl = 8 are shown. other cl values are 1. possible. shown with nominal 2. t dqsck and nominal t dsdq.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 90 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product the mode register 1 (mr1) controls additional functions and features not available in the other mode registers; q off (output d isable), dll enable/dll disable, r tt _nom value (odt), write leveling, posted cas additive latency, and output drive strength. these functions are controlled via the bits shown in figure 46 below. the mr1 register is programmed via the mr5 command and retains the store d information until it is reprogrammed, until reset\ goes low (true), or until the device loses power. reprogramming the mr1 register will not alter the contents of the memory array, provided the operation is performed correctly. the mr1 register must be loaded when all banks are idle and no bursts are in progress. the controller must satisfy the speci ed timing parameters t mrd and t mod before initiating a subsequent operation. mode register 1 (mr1) f igure 46- m ode r egister 1 (mr1) d efinition al r tt q off a9 a7 a6 a5 a4 a3 2 a 8 aa1 a0 mode register 1 (mr1) address bus 9 7 6 5 4 3 2 810 a10 a12 a11 1 a b 0 a b 3 1 2 1 1 1 0 1 m0 0 1 dll enable enable (normal) disable m5 0 0 1 1 output drive strength rzq/6 (40 [nom]) rzq/7 (34 [nom]) reserved reserved 14 wl 1 s d o 0 dll r tt tdqs m12 0 1 q off enabled disabled ba2 15 0 1 m7 0 1 write levelization disable (normal) enable additive latency (al) disabled (al = 0) al = cl - 1 al = cl - 2 reserved m3 0 1 0 1 m4 0 0 1 1 r tt ods m1 0 1 0 1 a13 16 0 1 m11 0 1 tdqs disabled enabled 0 1 0 1 r tt _ nom (odt) 2 non-writes r tt _ nom disabled rzq/4 (60 [nom]) rzq/2 (120 [nom]) rzq/6 (40 [nom]) rzq/12 (20 [nom]) rzq/8 (30 [nom]) reserved reserved r tt _ nom (odt) 3 writes r tt _ nom disabled rzq/4 (60 [nom]) rzq/2 (120 [nom]) rzq/6 (40 [nom]) n/a n/a reserved reserved m2 0 1 0 1 0 1 0 1 m6 0 0 1 1 0 0 1 1 m9 0 0 0 0 1 1 1 1 mode register mode register set 0 (mr0) mode register set 1 (mr1) mode register set 2 (mr2) mode register set 3 (mr3) m14 0 1 0 1 m15 0 0 1 1 notes: mr1[16, 13, 10, 8] are reserved for future use and must be programmed to ?0.? 1. during write leveling, if mr1[7] and mr1[12] are ?1? then all r 2. tt _nom values are available for use. during write leveling, if mr1[7] is a ?1,? but mr1[12] is a ?0,? then only r 3. tt _nom write values are available for use.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 91 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product the dll may be enabled or disabled by programming mr1[0] during the load mode command, as shown in figure 46 (previous page). the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation after having disabled the dll for the purpose of debugging or evalua- tion. enabling the dll should always be followed by resetting the dll using the appropriate load mode command. if the dll is enabled prior to entering self refresh mode, the dll is automatically disabled when entering self refresh operation and is automatically re-enabled and reset upon exit of self refresh. if the dll is disabled prior to entering self refresh, the dll remains disabled even upon exit of the self refresh operation until it has been re-enabled and reset. the sdram is not tested, nor does ldi warrant compliance with normal mode timings or functionality when the dll is disabled. an attempt has been made for the sdram to operate in the normal mode whenever possible when the dll is disabled; however, by industry standards, the following exceptions have been observed, de ned and listed: odt is not allowed to be used 1. the output data is no longer edge-aligned to the clock 2. cl and cwl can only be six clocks 3. when the dll is disabled, timing and functionality can vary from the normal operational speci cations when the dll is enabled. dis- abling the dll also implies the need to change the clock frequency. dll enable/dll disable odt resistance r tt _nom is de ned by mr1[9,6,2] (see figure 46). the r tt termination value applies to the dqx, ldmx, udmx, l[u]dqsx and l[u]dqsx\. the ddr3 device architecture supports multiple r tt termi- nation values based on rzq/n where n can be 3,4,6,8 or 12 and rzq is 240 . unlike ddr2, ddr3 odt must be turned off prior to reading data out and must remain off during read burst. r tt _nom termination is allowed any time after the dram is initialized, calibrated, and not performing read accesses, or in self refresh mode. additionally, write accesses with dynamic odt enabled (r tt _wr) temporarily replaces r tt _nom with r tt _wr. the actual effective termination, r tt _eff, may be different from the r tt targeted value due to non-linearity of the termination. for r tt _eff values and calculations, see the on-die termination (odt) description later in this ds. the odt feature is designed to improve signal integrity of the memory device by enabling the ddr3 sdram controller to independently turn on/ off odt for any or all devices in the end designs array. the odt input control pin is used to determine when r tt is turned on (odtlon) and off (odtloff), assuming odt has been enabled via mr1[9,6,2]. timings for odt are detailed in the ?on-die termination (odt)? descrip- tion later in this ds. on-die termination (odt) the ddr3 sdram imod uses a programmable impedance output buffer. the drive strength mode register setting is de ned by mr1[5:1], rzq/7 (34 [nom]) is the primary output driver impedance setting for the device. to calibrate the output driver impedance, and external precision resistor (rzq) is connected between the zq ball and vssq. the value of the resistor is 240 1%. the output impedance is set during initialization. additional impedance calibration updates do not affect device operation and all data sheet tim- ings and current speci cations are met during an update. to meet the 34 speci cation, the output drive strength must be set to 34 during initialization. to obtain a calibrated output driver impedance after power-up, the ddr3 imod sdram needs a calibration command that is part of the initialization and reset procedure. output drive strength the output enable function is de ned by mr1[12], as shown in figure 46. when enabled (mr1[12]=0), all outputs (dqx, dqsx, dqsx\) are tri-stated. the output disable feature is intended to be used during icc characterization of the read current and during t dqss margining (write leveling) only. output enable/disable the write leveling function is enabled by mr1[7], as shown in figure 46, write leveling is used (during initialization) to de-skew the dqsx strobe to clock offset as a result of y-by topology designs. for better signal integrity, some end use designs of ddr3 devices adopted y-by topology for the commands, addresses, control signals and clocks. the y-by topology bene ts from a reduced number of stubs and their lengths, however, y-by topology induces ight time skew between the clock and dqsx strobe (and dqx) at each sdram in the array. control- lers will have a dif cult time maintaining t dqss, t dss and t dsh speci ca- tions without supporting write leveling in systems which use y-by topology based designs. write leveling timing and detailed operation information is provided in ?write leveling. write leveling
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 92 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product al is supported to make the command and data bus ef cient for sustainable bandwidths in ddr3 srams. mr1[4,3] de ne the value of al (see figure 46). mr1[4,3] enables the user to program the ddr3 sdram with an al=0, cl-1, or cl-2. with this feature, the ddr3 sdram enables a read or write command to be issued after the activate command for that bank prior t o t rcd(min). the only restriction is activate to read or write + al t rcd(min) must be satis ed. assuming t rcd(min) = cl, a typical application using this feature, sets al=cl ? 1 t ck = t rcd(min-1 t ck. the read or write command is held for the time of the al before it is released internally to the ddr3 sdram imod device. read latency (rl) is controlled by the sum of the al and cas latency (cl), rl=al+cl, write latency (wl) is the sum of cas write latency and al, wl=al + cwl (see ?mode register 2 (mr2))?. examples of read and write latencies are shown in figure 47 and figure 49. posted cas additive latency (al) f igure 47- read l atency (al = 5, cl = 6) ck ck# command dq dqs, dqs# active n t0 t1 dont care nop nop t6 t12 nop read n t13 nop do n+ 3 do n + 2 do n + 1 rl = al + cl = 11 t14 nop do n t rcd (min) al = 5 cl = 6 t11 bc4 indicates a break in time scale transitioning data t2 nop
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 93 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 48- m ode r egister 2 (mr2) d efinition notes: 1. mr2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to 0. m14 0 1 0 1 m15 0 0 1 1 mode register mode register set 0 (mr0) mode register set 1 (mr1) mode register set 2 (mr2) mode register set 3 (mr3) a9 a7 a 6 a5 a4 a3 a8 a2 a1 a0 mode register 2 (mr2) add ress bus 976543 8210 a10 a12 ) ) * ) * $ % +3 / *) )1 ) 1 2 22 4 3 * 3 9 "1 : # -:
.
* :8 ' 3 9 4 " =, &= , # .; " =, (&= , # , *3 5 : 0 8< " ,50 # &, / " , / > & # , / " & ) , / > '& # ', / " '& ) , / > & # , / " & ) , / > & # % & ( -< :8 1 - 4 " 44 7 5 # 44 7 5 : 6 2 $% 6 2 $ the mode register 2 (mr2) controls additional functions and features not available in the other mode registers. these addition al functions are cas write latency (cwl), auto self refresh (asr), self refresh temperature (srt) and dynamic odt (r tt _wr). these functions are con- trolled via the bits shown in figure 48. the mr2 is programmed via the mrs command and will retain the stored information unti l it is programmed again or until the device loses power. reprogramming the mr2 register will not alter the contents of the memory array, provided that th e operation has been performed correctly. the mr2 register must be loaded when all banks are idle and no data bursts are in progress and the memory controlle r must wait for the speci ed time t mrd and t mod before initiating a subsequent operation. mode register 2 (mr2)
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 94 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 49- cas w rite l atency ck ck# command dq dqs, dqs# active n bc4 t0 t1 dont care nop nop t6 t12 nop write n t13 nop di n + 3 di n + 2 di n + 1 t14 nop di n t rcd (min) nop al = 5 t11 indicates a break in time scale wl = al + cwl = 11 transitioning data t2 cwl = 6 cwl is de ned by mr2[5:3] and is the delay, in clock cycles, from the releasing of the internal write to the latching of the rst data in. cwl must be correctly set to the corresponding operating clock frequency (see figure 48). the overall write latency (wl) is equal to cwl + al (see f igure 46). cas write latency (cwl) mode register mr2[6] is used to disable/enable the asr function. when asr is disabled, the self refresh mode?s refresh rate is assumed to be at the normal 85 ? c limit (commonly referred to as the 1x refresh rate). in the disabled mode, asr requires the user to ensure the sdram never exceeds a tc of 85 ? c while in self refresh unless the user enables the srt feature listed below, supporting an ele- vated temp up to +95 ? c while in self refresh. the standard self refresh current test speci es test conditions to normal case temperature (85 ? c) only, meaning if asr is enabled, the standard self refresh current speci cation does not apply (see the ?extended temperature usage? description later in this ds). auto self refresh (asr) optional extended temperature range of +95 ? c while in self refresh mode. the standard self refresh current test speci es test conditions to normal case temperature (85 ? c) only, meaning if srt is enabled, the standard self refresh current speci cations do not apply. srt vs. asr mode register mr2[7] is used to disable/enable the srt function. when srt is disabled, the self refresh mode?s refresh rate is assumed to be at the normal 85 ? c limit. in the disabled mode, srt requires the user to ensure the sdram never exceeds the tc limit of 85 ? c while in self refresh mode unless the user enables asr. when srt is enabled, the sdram self refresh is changed internally from 1x to 2x, regardless of the case temperature (tc). this enables the user to operate the sdram beyond the standard 85 ? c limit up to the self refresh temperature (srt) if the normal case temperature limit of 85 ? c is not exceeded, then neither srt nor asr is required, and both can be disabled throughout opera- tion. if the extended temperature option is used, the user is required to pro- vide a 2x refresh rate during (manual) refresh for extended temp devices or 3x refresh rate for mil-temp devices. srt and asr should be enabled for automatic refresh services on all devices used in temperature envi- ronments 95 ? c srt forces the sdram to switch the internal self refresh rate from 1x to 2x. self refresh is performed at 2x regardless of tc. asr automatically switches the sdram?s internal self refresh rate from 1x to 2x, however, while in self refresh mode, asr enables the refresh rate automatically adjust between 1x and 2x refresh rate over the supported temperature range. one other disadvantage with asr is the sdram cannot always switch from a 1x to a 2x refresh rate at an exact case temperature of 85 ? c. although the sdram will support data integrity when it switches from a 1x to 2x rate, it may switch at a lower temperature than 85 ? c. since only one mode is necessary at one instant in time, srt and asr cannot be simultaneously enabled.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 95 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product dynamic odt the mode register 3 (mr3) controls additional functions and features not available via mr0, mr1 or mr2. currently de ned as the multipurpose regis- ter (mpr). this function is controlled via the bits shown in figure 50. the mr3 is programmed via the load mode command and r etains the stored infor- mation until it is programmed again or until the device loses power. reprogramming the mr3 register will not alter the content s of the memory array, provided the programming of the mr3 has been performed correctly. the mr3 register must be loaded when all banks are idle and no data b ursts are in progress and the memory controller must wait the speci ed time t mrd and t mod before initiating a subsequent operation. mode register (mr3) the dynamic odt (r tt _wr) feature is de ned by mr2[10,9]. dynamic odt is enabled when a value is selected. this new ddr3 feature enables the odt termination value to change without issuing an mrs command, essentially changing the odt termination ?on-the- y?. with dynamic odt (r tt _wr) when beginning a write burst and subsequently switches back to odt (r tt _wr) is enabled: odtlcnw, odtlcnw4, odtlcnw* odth4, odth8 and t adc. dynamic odt is only applicable during write cycles, if odt (r tt _nom) is disabled, dynamic odt (r tt _wr) is still permitted. r tt _nom and r tt _wr can be used independent of one another. dynamic odt is not available during write leveling mode, regardless of the state of odt (r tt _nom). for details on odt operation, refer to the ?on-die-termination (odt)? section. f igure 50 - m ode r egister 3 (mr3) d efinition a9 a7 a 6 a5 a4 a3 a8 a2 a1 a0 mode register 3 (mr3) add ress bus 976543 8210 a10 a12 a11 1 a b0 a b 10 11 1 2 13 14 15 a13 10 1 0 1 0 1 0 1 0 1 0 1 0 1 mpr 1 ba2 16 0 1 0 1 0 1 0 1 0 1 m2 0 1 mpr enable normal dram operations 2 dataflow from mpr mpr_rf m14 0 1 0 1 m15 0 0 1 1 mode register mo de register set (mr0) mode register set 1 (mr1) mode register set 2 (mr2) mode register set 3 (mr3) mpr read func tion predefined pattern 3 reserved reserved reserved m0 0 1 0 1 m1 0 0 1 1 notes: mr3[16 and 13:4] are reserved for future use and must all be programmed to ?0.? 1. when mpr control is set for normal dram operation, mr3[1, 0] will be ignored. 2. intended to be used for read synchronization. 3.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 96 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product multipurpose register (mpr) the multipurpose register function is used to output a prede ned system timing calibration bit sequence. bit 2 is the master bit that enables or disables access to the mpr register and bits 1 and 0 determine which mode the mpr is placed in. the basic concept of the multipurpose r egister is shown in figure 51. if mr3[2] is a ?0?, then the mpr access is disabled and the sdram operates in normal mode. however, if mr3[2] is a ?1?, then sd ram no longer outputs normal read data but outputs mpr data as de ned by mr3[0,1]. if mr3[0,1] is equal to ?00?, then a prede ned read pattern for system calibration is selected. to enable the mpr, the mrs command is issued to mr3 and mr3[2]=1 (see table 66). prior to issuing the mrs command, all banks m ust be in the idle state (all banks are precharged, and t rp is met). when the mpr is enabled, any subsequent read or rdap commands are redirected to the multipurpose register. the resulting operation when either a read or a rdap command is issued is de ned by mr3[1:0]when mpr is enabled (see table 67). when the mpr is enabled, only read or rdap commands are allowed until a subsequent mrs command is issued with the mpr disabled (mr3[2]=0). pow er-down, self refresh and any other non read or rdap command is not allowed. the reset function is supported during mpr enable mode. f igure 51 - m ultipurpose r egister (mpr) b lock d iagram memory core mr3[2] = 0 (mpr off) dq, dm, dq s, dqs# multipurpose register pre defined data for reads mr3[2] = 1 (mpr on) notes: a prede ned data pattern can be read out of the mpr with an external read command. 1. mr3[2] de nes whether the data ow comes from the memory core or the mpr. when the data 2. ow is de ned, the mpr contents can be read out continuously with a regular read or rdap command.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 97 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product mpr mpr read function function 0 1 normal operation, no mpr transaction. all subsequent reads come from the sdram memory array. all subsequent writes go to the sdram memory array. enable mpr mode, subsequent read/rdap commands de ned by bits 1 and 2. t able 66: burst order ?don?t care? a[1:0] (see table 66) mr3[2] mr3[1:0] mpr functional description the mpr jedec de nition allows for either a prime dq0 for lower byte and dq8 for the upper byte of each of the (4) words contained in the ldi im od, to output the mpr data with the remaining dqs driven low, or for all dqs to output the mpr data. the mpr readout supports xed read burst and read burst chop (mrs and otf via a12/bc#) with regular read latencies and ac timings applicable. this providing the dll is locked as required. mpr addressing for a valid mpr read is as follows: a[1:0] must be set to ?00? as the burst order is xed per nibble ? a2 selects the burst order ? bl8, a2 is set to ?0?, and the burst order is xed to 0,1,2,3,4,5,6,7 ? for burst chop 4 cases, the burst order is switched on the nibble base and: ? a2=0: burst order =0,1,2,3 ? a2=1: burst order =4,5,6,7 ? burst order bit 0 (the rst bit) is assigned to lsb, and burst order bit 7 (the last bit) is assigned to msb ? a[9:3] are a ?don?t care? ? a10 is a ?don?t care? ? a11 is a ?don?t care? ? a12: selects burst chop mode on-the- y, if enabled within mr0 ? a13 is a ?don?t care? ? ba[2:0] are a ?don?t care? ?
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 98 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product mpr register address definitions and bursting order the mpr currently supports a single data format. this data format is a prede ned read pattern for system calibration. the prede ned pattern is always a repeating 0-1 bit pattern. examples of the different type of prede ned read pattern bursts are shown in figures 52, 53, and 54. mr3[2] mr3[1:0] function length a[2:0] burst order and data pattern 1 1 1 1 burst order: 0,1,2,3,4,5,6,7 prede ned pattern: 0,1,0,1,0,1,0,1 burst order: 0,1,2,3 prede ned pattern: 0,1,0,1 burst order: 4,5,6,7 prede ned pattern: 0,1,0,1 n/a n/a n/a n/a n/a n/a n/a n/a n/a t able 67: burst order read prede ned pattern for system calibration rfu rfu rfu bl8 bc4 bc4 n/a n/a n/a n/a n/a n/a n/a n/a n/a 000 000 100 n/a n/a n/a n/a n/a n/a n/a n/a n/a 00 01 10 11 burst read
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 99 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product notes: 1. read with bl8 either by mrs or otf. 2. memory controller must drive 0 on a[2:0]. t0 ta0 tb0 tb 1 tc0 tc1 tc2 tc3 tc4 tc5 tc 6 tc7 tc8 tc9 tc1 0 ck ck # mrs prea read 1 nop nop nop nop nop nop nop nop mrs nop nop valid command t mprr don t care indicates a break in time scale dqs, dqs# bank add ress 3 vali d 3 0 a[1:0] vali d 0 2 1 a2 0 2 0 00 a[9:3] vali d 00 0 1 a10/ap vali d 0 0i l a v 1 1 a d 0 0 a12/bc# vali d 1 0 0i l a v ] 3 1 : 5 1 [ a d 0 dq t mod t rp t mod rl figure 52 - mpr system read calibration with bl8: fixed burst order single readout
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 100 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product notes: 1. read with bl8 either by mrs or otf. 2. memory controller must drive 0 on a[2:0]. t0 ta tb tc0 tc1 tc2 tc3 tc4 tc5 tc 6 tc7 tc8 tc9 tc1 0 td ck ck# t mprr don t care indicates a break in time scale rl 3 vali d 3 bank add ress vali d a[1:0] vali d 0 2 0 2 0 a2 1 2 0 2 1 0 0 a[15:13] vali d vali d 0 a[9:3] vali d vali d 00 00 a11 vali d vali d 0 0 a12/bc# vali d 1 0 0 a10/ap vali d vali d 0 0 1 rl prea read 1 nop nop nop no nop nop nop mrs vali d command read 1 mrs dq vali d dqs, dqs# t rp t mod t ccd t mod nop nop figure 53 - mpr system read calibration with bl8: fixed burst order, back-to-back readout
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 101 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product notes: 1. read with bc4 either by mrs or otf. 2. memory controller must drive 0 on a[1:0]. 3. a2 = 0 selects lower 4 nibble bits 0 . . . 3. 4. a2 = 1 selects upper 4 nibble bits 4 . . . 7. t0 ta tb ck ck# dq dqs, dqs# t mod t mprr don t care tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 tc8 tc9 tc10 td nop nop nop nop valid command mrs prea read 1 read 1 nop nop indicates a break in time scale bank add ress 3 vali d 3 vali d 0 a[1:0] vali d 0 2 0 2 1 a2 1 4 0 3 0 00 i l a v ] 3 : 9 [ a d vali d 00 0 1i l a v p a / 0 1 a d vali d 0 0i l a v 1 1 a d vali d 0 0 a12/bc# vali d 1 vali d 1 0 0 a[15:13] vali d vali d 0 rl rl t rf t mod t ccd nop nop mrs nop figure 54 - mpr system read calibration with bc4: lower nibble, then upper nibble
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 102 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product notes: 1. read with bc4 either by mrs or otf. 2. memory controller must drive 0 on a[1:0]. 3. a2 = 1 selects upper 4 nibble bits 4 . . . 7. 4. a2 = 0 selects lower 4 nibble bits 0 . . . 3. t0 ta tb 0 1i l a v p a / 0 1 a dvalid 0 ck ck# mrs prea read 1 read 1 nop nop nop s nop nop valid command 0 0 4 1 3 1 a2 t mod t mprr 3valid 3 bank add ress vali d 0 2 0 2 0 a[1:0] vali d 0 0i l a v ] 3 1 : 5 1 [ a dvalid 0 0i l a v 1 1 a d vali d 00 00 i l a v ] 3 : 9 [ a dvalid don t care tc 0 tc1 tc2 tc3 tc4 tc5 tc 6 tc7 tc8 tc9 tc1 0 td indicates a break in time scale rl dq dqs, dqs# 0 a12/bc# vali d 1 vali d 1 0 rl t rf t mod t ccd mr nop nop nop nop figure 55 - mpr system read calibration with bc4: upper nibble, then lower nibble
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 103 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product mpr read predefined pattern the predetermined read calibration pattern is a xed pattern of 0,1,0,1,0,1,0,1. the following is an example of using the read out predetermined read calibration pattern. the example is to perform multiple reads from the multipurpose register (mpr) in order to do system level read timing calibra- tion based on the predetermined and standardized pattern. the following protocol outlines the steps used to perform the read calibration: precharge all banks ? after ? t rp is satis ed, set mrs, mr3[2] = 1 and mr3[1:0]=00. this redirects all subsequent reads and loads the prede ned pattern into the mpr. as soon as t mrd and t mod are satis ed, the mpr is available. data write operations are not allowed until the mpr returns to the normal sdram state ? issue a read with burst order information (all other address pins are ?don?t care?): ? a[1:0] = 00 (data burst order is xed starting at nibble) ? a2 = 0 (for bl8, burst order is xed as 0,1,2,3,4,5,6,7) ? a12 = 1 (use bl8) ? after rl = al + cl, the sdram bursts out the prede ned read calibration pattern (0,1,0,1,0,1,0,1) ? the memory controller repeats the calibration reads until read data capture at the memory controller is optimized ? after the last mpr read burst and after ? t mprr has been satis ed, issue mrs, mr3[2] = 0 and mr3[1:0] = ?don?t care? to the normal sdram state. all subsequent read and write accesses will be regular reads and writes from/to the sdram array when ? t mrd and t mod are satis ed from the last mrs, the regular sdram commands (such as activate a memory bank for regular read or write access) are permitted mode register set (mrs) the mode registers are loaded via inputs ba[2:0], a[13:0]. ba[2:0] determines which mode register is programmed: ba2 = 0, ba1 = 0, ba0 = 0 for mr0 ? ba2 = 0, ba1 = 0, ba0 = 1 for mr1 ? ba2 = 0, ba1 = 1, ba0 = 0 for mr2 ? ba2 = 0, ba1 = 1, ba0 = 1 for mr3 ? the mrs command can only be issued (or reissued) when all banks are idle and in the precharged state ( t rp is satis ed and no data bursts are in progress). the controller must wait the speci ed time t mrd before initiating a subsequent operation such as an activate command. there is also a restriction after issuing an mrs command with regard to when the updated functions become available. this parameter is speci ed by t mod. both t mrd and t mod parameters are shown in figure 42 and 43. violating either of these requirements will result in unspeci ed operation. zq calibration the zq calibration command is used to calibrate the sdram output drivers (ron) and odt values (r tt ) over process, voltage, and temperature, pro- vided a dedicated 240 (1%) external resistor is connected from the sdram?s zq ball to vssq. ddr3 sdrams need a longer time to calibrate r on and odt at power up initialization and self refresh exit and a relatively shorter time to perform periodic calibrations. ddr3 sdram de nes two zq calibration commands: zq calibration long (zqcl) and zq calibration short (zqcs). an example of zq calibration timing is shown in figure 56. all banks must be precharged and t rp must be met before zqcl or zqcs commands can be issued to the sdram. no other activities (other than another zqcl or zqcs command may be issued to the sdram) can be performed on the sdram array by the controller for the duration of t zqinit or t zqoper. the quiet time on the sdram array helps accurately calibrate r on and odt. after sdram calibration is achieved, the sdram should disable the zq ball?s current consumption path to reduce overall power usage. zq calibration commands can be issued in parallel to dll reset and locking time. upon self refresh exit, an explicit zqcl is r equired if zq cali- bration is desired. in dual rank system designs that share the zq resistor between devices, the controller must not allow overlap of t zqint, t zqoper or t zqcs between ranks.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 104 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 56 - zq c alibration t iming (zqcl and zqcs) nop zqcl nop nop valid vali d zqcs nop nop nop valid command indicates a break in time scale t0 t1 ta0 ta1 ta2 ta3 tb0 tb1 tc0 tc1 tc2 address vali d vali d vali d a10 vali d vali d vali d ck ck# don t care dq high-z high-z 3 a 3 ctivities activ- ities vali d vali d odt 2 2 vali d 1 ck e 1 vali d vali d vali d t zqcs t zq init or t zq oper notes: cke must be continuously registered high during the calibration procedure. 1. odt must be disabled via the odt signal or the mrs during the calibration procedure. 2. all devices connected to the dq bus should be high-z during calibration. 3. activate before any read or write commands can be issued to a bank within the sdram, a row in that bank must be opened (activated). thi s is accomplished via the activate command, which selects both the bank and the row to be activated. after a row is opened with an activate command, a read or write command may be issued to that row, subject to the t rcd speci cation. however, if the additive latency is programmed correctly, a read or write command may be issued prior to t rcd (min). in this operation, the sdram enables a read or write command to be issued after the activate command for that bank, but prior to t rcd (min) (see ?posted cas additive latency (al)). t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the activate command on which the read or write command can be entered. the same procedure is used to convert other speci cation limits from time units to clock cycles. when at least one bank is open, any read-to-read command delay or write-to-write command delay is restricted to t ccd (min). a subsequent activate command to a different row in the same bank can only be issued after the previous active row has been clo sed (pre- charged). the minimum time interval between successive activate commands to the same bank is de ned by t rc. a subsequent activate command to another bank can be issued while the rst bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive activate commands may be issued in a given t faw (min) period, and the t rrd (min) restriction still applies. the t faw (min) parameter applies, regardless of the number of banks already opened or closed.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 105 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 57 - e xample : m eeting t rrd (min) and t rcd (min) command don t care t1 t0 t2 t3 t4 t5 t8 t9 t rrd row row co l bank x bank y bank y nop act nop nop act nop nop rd/wr t rcd ba[2:0] ck # add ress ck t10 t11 nop nop indicates a break in time scale f igure 58 - e xample : t faw command don t care t1 t0 t4 t5 t8 t9 t10 t11 t rrd row row bank a bank b row bank c row bank d bank y row bank y nop act nop ac a tctnop nop t faw ba[2:0] ck # add ress ck t19 t20 nop ac a tct bank e indicates a break in time scale
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 106 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 59 - read l atency notes: 1. do n = data-out from column n. 2. subsequent elements of data-out appear in the programmed order following do n. . ck ck # command read nop nop nop nop nop nop nop add ress bank a, col n cl = 8, al = 0 dq dqs, dqs# do n t0 t7 t8 t9 t10 t11 don t care transitioning data t12 t12 indicates a break in time scale read read bursts are initiated with a read command. the starting column and bank addresses are provided with the read command and a uto pre- charge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is automatica lly precharged at the completion of the burst sequence. if auto precharge is disabled, the row will be left open after the completion of the bur st. during read bursts, the valid data out element from the starting column address is available at read latency (rl) clocks later. rl is de ned as the sum of posted cas additive latency (al) and cas latency (cl) (rl = al + cl). the value of al and cl is programmable in the mode re gister via the mrs command. each subsequent data-out element will be valid nominally at the next positive or negative clock edge (that is, at the next crossing of ck and ck\). figure 59 shows an example of rl based on a cl setting of 8 as well as al=0. a read burst may be followed by a precharge command to the same bank provided auto precharge is not activated. the minimum read-to-precharge command spacing to the same bank is four clocks and must also satisfy a minimum analog time from the read command. this time is called t rtp (read-to-precharge). t rtp starts al cycles later than the read command. examples for bl8 are shown in figure 65 and bc4 in figure 66. following the precharge command, a subse- quent command to the same bank cannot be issued until t rp is met. the precharge command followed by another precharge command to the same bank is allowed. however, the precharge period will be deter- mined by the last precharge command issued to the bank. if a10 is high when a read command is issued, the read with auto precharge function is engaged. the sdram starts an auto pre- charge operation on the rising edge which is al + t rtp cycles after the read command. ddr3 sdrams support a t ras lockout feature (see figure 68). if t ras (min) is not satis ed at the edge, the starting point of the auto precharge operation will be delayed until t ras (min) is sat- is ed. in case the internal precharge operation is pushed out by t rtp, t rp starts at the point at which the internal precharge happens. the time from read with auto precharge to the next activate com- mand the same bank is al + ( t rtp + t rp)*, where ?*? means rounded up to the next integer. in any event, internal recharge does not start earlier than four clocks after the last 8n-bit prefetch. l[u]dqsx, l[u]dqsx\ is driven by the sdram along with the output data. the initial low state on l[u]dqsx and high state on l[u]dqsx\, is known as the read preamble ( t rpre). the low state on dqsx and the high state on l[u]dqsx\, coincident with the last data-out element, is known as the read postamble ( t rpst). upon completion of a burst, assuming no other commands have been initiated, the dq will go high-z. a detailed explanation of t dqsq (valid data-out skew), t qh (data-out window hold), and the valid data window are depicted in figure 71. a detailed explanation of t dqsck (dqs transition skew to ck) is also depicted in figure 71. data from any read burst may be concatenated with data from a subse- quent read command to provide a continuous ow of data. the rst data element from the new burst follows the last element of a completed burst. the new read command should be issued t ccd cycles after the rst read command. this is shown for bl8 in figure 60. if bc4 is enabled, t ccd must still be met which will cause a gap in the data output, as shown in figure 61. nonconsecutive read data is re ected in figure 62. ddr3 sdrams do not allow interrupting or truncating any read burst. data from any read burst must be completed before a subsequent write burst is allowed. an example of a read burst followed by a write burst for bl8 is shown in figure 63. to ensure the read data is completed before the write data is on the bus, the minimum read-to-write timing is rl + t ccd ? wl + 2 t ck.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 107 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during read command at t0 and t4. 3. do n (or b) = data-out from column n (or column b). 4. bl8, rl = 5 (cl = 5, al = 0). t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 don t care transitioning data t12 t13 t14 t rpst nop d a e r d a e r p o n p o n p o n p o n p o n p o n p o n p o n p o n p o n p o n p o n ck ck# c ommand 1 dq 3 dqs, dqs# bank, col n bank, co l b add ress 2 rl = 5 t rpre t ccd rl = 5 do n+ 3 do n+ 2 do n + 1 do n do n+ 7 do n + 6 do n + 5 do n+ 4 do b + 3 do b + 2 do b+ 1 do b do b + 7 do b + 6 do b + 5 do b+ 4 figure 60 - consecutive read bursts (bl8)
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 108 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bc4 setting is activated by either mr0[1:0] = 10 or mr0[1:0] = 01 and a12 = 0 during read command at t0 and t4. 3. do n (or b) = data-out from column n (or column b). 4. bc4, rl = 5 (cl = 5, al = 0). nop ck ck# comman d 1 dq 3 dqs, dqs# t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 address 2 t10 t11 don t care transitioning data t12 t13 t14 read read nop nop nop nop nop nop nop nop nop nop nop nop bank, col n bank, col b t rpst t rpre t rpst t rpre rl = 5 do n+ 3 do n + 2 do n + 1 do n do b+ 3 do b+ 2 do b+ 1 do b rl = 5 t ccd figure 61 - consecutive read bursts (bc4)
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 109 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product notes: 1. al = 0, rl = 8. 2. do n (or b) = data-out from column n (or column b). 3. seven subsequent elements of data-out appear in the programmed order following do n. 4. seven subsequent elements of data-out appear in the programmed order following do b. don t care transitioning data t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 dqs, dqs# command nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop read nop read add ress bank a, co l n bank a, col b ck ck # dq do n do b c l = 8 c l = 8 figure 62 - nonconsecutive read bursts
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 110 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during the read command at t0, and the write command at t6. don t care transitioning data t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 ck ck # command 1 nop nop nop nop nop write nop nop nop nop nop nop nop nop nop t wpst t rpre t wpre t rpst dqs, dqs# dq 3 wl = 5 t wr t wtr read do n do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 di n di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 read-to-write command delay = rl + t ccd + 2 t ck - wl t bl = 4 clocks add ress 2 bank, col b bank, col n rl = 5 figure 63 - read (bl8) to write (bl8)
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 111 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bc4 otf setting is activated by mr0[1:0] and a12 = 0 during read command at t0 and write command at t4. 3. do n = data-out from column n; di n = data-in from column b. 4. bc4, rl = 5 (al - 0, cl = 5), wl = 5 (al = 0, cwl = 5). don t care transitioning data t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 ck ck# add ress 2 bank, col n bank, col b command 1 read nop nop nop write nop nop nop nop nop nop nop nop nop nop nop t wpst t wpre t rpst dqs, dqs# dq 3 wl = 5 read-to-write command delay = rl + t cc d/2 + 2 t ck - wl t wr t wtr t bl = 4 clo cks t rpre rl = 5 do n do n+ 1 do n+ 2 do n + 3 di n di n + 1 di n + 2 di n+ 3 figure 64 - read (bc4) to write (bc4) otf
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 112 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during the read command at t0, and the write command at t6. 3. do n = data-out from column, di b = data-in for column b. 4. bl8, rl = 5 (al = 0, cl = 5), wl = 5 (al = 0, cwl = 5). don t care transitioning data t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 ck ck # command 1 nop nop nop nop nop write nop nop nop nop nop nop nop nop nop t wpst t rpre t wpre t rpst dqs, dqs# dq 3 wl = 5 t wr t wtr read do n do n + 1 do n + 2 do n + 3 do n + 4 do n + 5 do n + 6 do n + 7 di n di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 di n + 7 read-to-write command delay = rl + t ccd + 2 t ck - wl t bl = 4 clocks add ress 2 bank, col b bank, col n rl = 5 figure 65 - read to precharge (bl8)
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 113 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product ck ck# don t care transitioning data t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 command nop nop nop nop nop nop nop nop nop act nop nop nop nop nop read nop pre add ress bank a, col n bank a, (or all) bank a, row b t rp t rtp dqs, dqs# dq do n do n+ 1 do n+ 2 do n+ 3 t ras figure 66 - read to precharge (bc4)
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 114 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product ck ck# command dq dqs, dqs# active n t0 t1 dont care nop nop t6 t12 nop read n t13 nop do n+ 3 do n + 2 do n + 1 rl = al + cl = 11 t14 nop do n t rcd (min) al = 5 cl = 6 t11 bc4 indicates a break in time scale transitioning data t2 nop figure 67 - read to precharge (al = 5, cl = 6)
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 115 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product ck ck # command nop nop nop nop add ress dq dqs, dqs# don t care transitioning data nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 ta0 t rtp (min) nop read nop al = 4 nop nop cl = 6 nop t ras (min) act indicates a break in time scale t rp bank a, col n bank a, row b do n do n+ 1 do n+ 2 do n+ 3 figure 68 - read with auto precharge (al = 4, cl = 6)
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 116 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product a dqsx to dq output timing is shown in figure 69. the dq transitions between valid data outputs must be within t dqsq of the crossing point of l[u]dqsx, l[u]dqsx\. dqs must also maintain a minimum high and low time of t qsh and t qsl. prior to the read preamble, the dq balls will either be oating or terminated depending on the status of the odt signal. figure 70 shows the strobe-to-clock timing during a read. the crossing point dqsx, dqsx\ must transition with t dqsck of the clock crossing point. the data out has no timing relationship to clock, only to dqs, as shown in figure 70. figure 70 also shows the read preamble and postamble. normally, both dqsx and dqsx\ are high-z to save power (vccq). prior to data output from the sdram, dqsx is driven low and dqsx\ driven high for t rpre. this is known as the read preamble. the read postamble, t rpst, is one half clock from the last l[u]dqsx, l[u]dqsx\ transition. during the read postamble, l[u]dqsx is driven low and l[ u] dqsx\ driven high. when complete, the dq will either be disabled or will continue terminating depending on the state of the od t signal. figure 75 demon- strates how to measure t rpst. read
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 117 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1, 0] = 0, 0 or mr0[0, 1] = 0, 1 and a12 = 1 during read command at t0. 3. do n = data-out from column n. 4. bl8, rl = 5 (al = 0, cl = 5). 5. output timings are referenced to v cc q/2 and dll on and locked. 6. t dqsq defines the skew between dqs, dqs# to data and does not define dqs, dqs# to clock. 7. early data transitions may not always happen at the same dq. data transitions of a dq can vary (either early or late) within a burst. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 bank, col n t rpst nop read nop nop nop nop nop nop nop nop nop ck ck# command 1 add ress 2 t dqsq (max) dqs, dqs# dq 3 (last data valid) dq 3 (first data no lon ger valid) all dq collectively do n do n+ 3 do n + 2 do n+ 1 do n+ 7 do n+ 6 do n+ 5 do n+ 4 do n + 2 do n+ 1 do n+ 7 do n + 6 do n+ 5 do n+ 4 do n+ 3 do n+ 2 do n+ 1 do n do n+ 7 do n+ 6 do n+ 5 do n do n + 3 t rpre don t care transitioning data data valid data valid t qh t qh t hz (dq) max do n+ 4 rl = al + cl t dqsq (max) t lz (dq) min figure 69 - data output timing ? t dqsq and data valid window
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 118 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t hz and t lz transitions occur in the same access time as valid data transitions. these parameters are referenced to a speci c voltage level which speci es when the device output is no longer driving t hz (dqs) and t hz (dq) or begins driving t lz (dqs). t lz (dq), figure 71 shows a method to calculate the point when the device is not longer driving t hz (dqs) and t hz (dq) or begins driving t lz (dqs), t lz (dq) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. the parameters t lz (dqs), t lz (dq), t hz (dqs) and t hz (dq) are de ned as single-ended. output timing
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 119 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product rl measured to this point dqs, dqs# early strobe ck t dqsck (min) t lz (dqs) min t hz (dqs) min dqs, dqs# late strobe t dqsck (max) t lz (dqs) max t hz (dqs) max t dqsck (min) t dqsck (min) t dqsck (max) t dqsck (max) t dqsck (max) t dqsck (min) ck# t rpre t qsh t qsl t qsl t qsl t qsl t qsh t qsh t qsh bit 0 bit 1 bit 2 bit 7 t rpre bit 0 bit 1 bit 2 bit 7 bit 6 bit 3 bit 4 bit 5 bit 6 bit 4 bit 3 bit 5 t rpst t rpst t0 t1 t2 t3 t4 t5 t 6 figure 70 - data strobe timing ? reads
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 120 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product notes: 1. within a burst, the rising strobe edge is not necessarily fixed at t dqsck (min) or t dqsck (max). instead, the rising strobe edge can vary between t dqsck (min) and t dqsck (max). 2. the dqs high pulse width is defined by t qsh, and the dqs low pulse width is defined by t qsl. likewise, t lz (dqs) min and t hz (dqs) min are not tied to t dqsck (min) (early strobe case) and t lz (dqs) max and t hz (dqs) max are not tied to t dqsck (max) (late strobe case); however, they tend to track one another. 3. the minimum pulse width of the read preamble is defined by t rpre (min). the minimum pulse width of the read postamble is defined by t rpst (min). t hz (dqs), t hz (dq) t hz (dqs), t hz (dq) end point = 2 t1 - t2 v oh - xmv v tt - xmv v ol + xmv v tt + xmv v oh - 2xmv v tt - 2xmv v ol + 2xmv v tt + 2xmv t lz (dqs), t lz (dq) t lz (dqs), t lz (dq) begin point = 2 t1 - t2 t1 t1 t2 t2 figure 71 - method for calculating t lz and t hz
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 121 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 72 - t rpre t iming t rpre dqs - dqs# dqs dqs# t1 t rpre begins t2 t rpre ends ck ck # v tt resultin g differential signal relevant for t rpre specification t c t a t b t d 0v v tt v tt single-ended signal, provided as background information single-ended signal, provided as background information f igure 73 - t rpst t iming t rpst dqs - dqs# dqs dqs# t1 t rpst begins t2 t rpst ends resultin g differential signal relevant for t rpst specification ck ck # v tt t c t a t b t d single-ended signal, provided as background information 0v v tt v tt single-ended signal, provided as background information
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 122 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 74 - t wpre t iming dqs - dqs# t1 t wpre begins t2 t wpre ends t wpre resulting differential signal relevant for t wpre specification 0v ck ck# v tt f igure 75 - t wpst t iming t wpst dqs - dqs# t1 t wpst begins t2 t wpst ends resulting differential signal relevant for t wpst specification 0v ck ck # v tt
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 123 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product write write bursts are initiated with a write command. the starting column and bank addresses are provided with the write command, a nd auto pre- charge is selected, the row being accessed will be precharged at the end of write burst. if auto precharge is not selected, th e row will remain open for subsequent accesses. after a write command has been issued, the write burst may not be interrupted. for the generic write commands used in figure 76 though figure 84, auto precharge is disabled. during write bursts, the rst valid data-in element is registered on a rising edge of dqsx following the write latency (wl) clocks later and subsequent data elements will be registered on successive edges of dqsx. write latency (wl) is de ned as the sum of posted cas additive latency (al) and cas write latency (cwl): wl = al + cwl. the values of al and cwl are programmed in the mr- and mr2 registers, respectively. p rior to the rst valid dqsx edge, a full cycle is needed (including a dummy crossover of dqsx, dqsx\) and speci ed as the write preamble shown in figure 76. the half cycle on dqsx following the last data-in element is known as the write postamble. the time between the write command and the rst valid edge of dqsx is wl clocks t dqss. figure 77 through figure 84 show the nominal case where t dqss = 0ns; however, figure 76 includes t dqss (min) and t dqss (max) cases. data may be masked from completing a write using data mask. the mask occurs on the dm ball aligned to the write data. if dm i s low, the write completes normally. if dm is high, that bit of data is masked. upon completion of a burst, assuming no other commands have been initiated, the dq will remain high-z and any additional input data will be ignored. data for any write burst may be concatenated with a subsequent write command to provide a continuous ow of input data. the new write command can be t ccd clocks following the previous write command. the rst data element from the new burst is applied after the last element of a completed burst. figures 77 and 78 show concatenated bursts. an example of nonconsecutive writes is shown in figure 79. data for any write burst may be followed by a subsequent read command after t wtr has been met (see figures 80, 81 and 82). data for any write burst may be followed by a subsequent precharge command providing t wr has been met, as shown in figure 83 and figure 84. both t wtr and t wr starting time may vary depending on the mode register settings ( xed bc4, bl8 vs. otf).
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 124 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 76 - w rite b urst notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during the write command at t0. 3. di n = data-in for column n. 4. bl8, wl = 5 (al = 0, cwl = 5). 5. t dqss must be met at each rising clock edge. 6. t wpst is usually depicted as ending at the crossing of dqs, dqs#; however, t wpst actually ends when dqs no longer drives low and dqs# no longer drives high. di n + 3 di n + 2 di n + 1 di n t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 don t care transitioning data di n + 7 di n + 6 di n + 5 di n + 4 bank, col n nop write nop nop nop nop nop nop nop nop nop ck ck# c ommand 1 dq 3 dqs, dqs# add ress 2 t wpst t wpre t wpst t dqsl dq 3 dq 3 t wpst dqs, dqs# dqs, dqs# t dqsl t wpre t dqss t dqss t dsh t dsh t dsh t dsh t dss t dss t dss t dss t dss t dss t dss t dss t dss t dss t dsh t dsh t dsh t dsh t dqsl t dqsh t dqsl t dqsh t dqsl t dqsh t dqsh t dqsl t dqsl t dqsl t dqsl t dqsh t dqsh t dqsh t dqsh t dqsl t dqsh t dqsl t dqsh t dqsh t dqsl t dqsh t dqsl t dqsh t dqsl t dqsh t dqsh wl = al + cwl t dqss (min) t dqss (nom) t dqss (max) t dqsl t wpre di n + 3 di n + 2 di n + 1 di n di n + 7 di n + 6 di n + 5 di n + 4 di n + 3 di n + 2 di n + 1 di n di n + 7 di n + 6 di n + 5 di n + 4
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 125 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 77 - c onsecutive write (bl8) to write (bl8) notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and a12 = 1 during the write commands at t0 and t4. 3. di n (or b) = data-in for column n (or column b). 4. bl8, wl = 5 (al = 0, cwl = 5). wl = 5 wl = 5 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t ccd t wpre t10 t11 don t care transitioning data t12 t13 t14 valid valid nop write write nop nop nop nop nop nop nop nop nop nop nop nop ck ck# command 1 dq 3 dqs, dqs# add ress 2 t wpst t wr t wtr t bl = 4 clocks di n + 3 di n + 2 di n + 1 di n di n + 7 di n + 6 di n + 5 di n + 4 di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b + 5 di b + 4 f igure 78 - c onsecutive write (bc4) to write (bc4) via mrs or otf notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bc4, wl = 5 (al = 0, cwl = 5). 3. di n (or b) = data-in for column n (or column b). 4. the bc4 setting is activated by mr0[1:0] = 01 and a12 = 0 during the write command at t0 and t4. wl = 5 wl = 5 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t ccd t wpre t10 t11 don t care transitioning data t12 t13 t14 vali d vali d nop write write nop nop nop nop nop nop nop nop nop nop nop nop ck ck# command 1 dq 3 dqs, dqs# address 2 t wpst t wr t wtr t wpst t wpre di n + 3 di n + 2 di n + 1 di n di b + 3 di b + 2 di b + 1 di b t bl = 4 clo cks
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 126 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 79 - n onconsecutive write to write notes: 1. di n (or b) = data-in for column n (or column b). 2. seven subsequent elements of data-in are applied in the programmed order following do n. 3. each write command may be to any bank. 4. shown for wl = 7 (cwl = 7, al = 0). ck ck# c ommand nop nop nop add ress dq dm dqs, dqs# transitioning data nop nop nop nop nop nop nop nop nop nop t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 nop write nop write vali d vali d nop di n di n + 1 di n + 2 di n + 3 di n + 4 di n + 5 di n + 6 don't care di n + 7 di b di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 wl = c wl + al = 7 wl = c wl + al = 7 f igure 80 - write (bl8) to read (bl8) notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. t wtr controls the write-to-read delay to the same device and starts with the first rising clock edge after the last write data shown at t9. 3. the bl8 setting is activated by either mr0[1:0] = 00 or mr0[1:0] = 01 and mr0[12] = 1 during the write command at t0. the read command at ta0 can be either bc4 or bl8, depending on mr0[1:0] and the a12 status at ta0. 4. di n = data-in for column n. 5. rl = 5 (al = 0, cl = 5), wl = 5 (al = 0, cwl = 5). wl = 5 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t wpre t10 t11 don t care transitioning data ta0 nop write read vali d vali d nop nop nop nop nop nop nop nop nop nop ck ck# command 1 dq 4 dqs, dqs# add ress 3 t wpst t wtr 2 indicates a break in time scale di n + 3 di n + 2 di n + 1 di n di n + 7 di n + 6 di n + 5 di n + 4
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 127 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 81 - write to read (bc4 m ode r egister s etting ) notes: 1. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 2. t wtr controls the write-to-read delay to the same device and starts with the first rising clock edge after the last write data shown at t7. 3. the fixed bc4 setting is activated by mr0[1:0] = 10 during the write command at t0 and the read command at ta0. 4. di n = data-in for column n. 5. bc4 (fixed), wl = 5 (al = 0, cwl = 5), rl = 5 (al = 0, cl = 5). wl = 5 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 ta0 don t care transitioning data nop write vali d read vali d p o n p o n p o n p o n p o n p o n p o n nop ck ck# command 1 dq 4 dqs, dqs# add ress 3 t wpst t wtr 2 t wpre indicates a break in time scale di n + 3 di n + 2 di n + 1 di n
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 128 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 82 - write (bc4 otf) to read (bc4 otf) notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. t wtr controls the write-to -read delay to the same device and starts after t bl. 3. the bc4 otf setting is activated by mr0[1:0] = 01 and a 12 = 0 during the write command at t0 and the read command at tn. 4. di n = data-in for column n. 5. bc4, rl = 5 (al = 0, cl = 5), wl = 5 (al = 0, cwl = 5). wl = 5 rl = 5 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t wpre t10 t11 don t care transitioning data tn nop write read vali d vali d nop nop nop nop nop nop nop nop nop ck ck# c ommand 1 dq 4 dqs, dqs# add ress 3 t wpst t bl = 4 clo cks nop t wtr 2 indicates a break in time scale di n + 3 di n + 2 di n + 1 di n
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 129 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 83 - write (bl8) to precharge notes: 1. di n = data-in from column n. 2. seven subsequent elements of data-in are applie d in the programmed order following do n. 3. shown for wl = 7 (al = 0, cwl = 7). t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 ta0 ta1 di n + 3 di n + 2 di n + 1 di n di n + 6 di n + 7 di n + 5 di n + 4 nop write vali d nop nop nop nop nop nop nop nop nop nop nop nop pre ck ck # c ommand dq bl8 dqs, dqs# add ress don t care transitioning data indicates a break in time scale t wr wl = al + cwl vali d f igure 84 - write (bc4 m ode r egister s etting ) to precharge notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the write recovery time ( t wr) is referenced from the first rising clock edge after the last write data is shown at t7. t wr specifies the last burst write cycle until the precharge command can be issued to the same bank. 3. the fixed bc4 setting is activated by mr0[ 1:0] = 10 during the write command at t0. 4. di n = data-in for column n. 5. bc4 (fixed), wl = 5, rl = 5. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 ta0 ta1 di n + 3 di n + 2 di n + 1 di n nop write vali d nop nop nop nop nop nop nop nop nop nop nop nop pre ck ck # comman d dq bc4 dqs, dqs# add ress don t care transitioning data indicates a break in time scale t wr wl = al + cwl vali d
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 130 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 85 - write (bc4 otf) to precharge notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. the write recovery time ( t wr) is referenced from the rising clock edge at t9. t wr specifies the last burst write cycle until the precharge command can be issued to the same bank. 3. the bc4 setting is activated by mr0[1:0] = 01 and a12 = 0 during the write command at t0. 4. di n = data-in for column n. 5. bc4 (otf), wl = 5, rl = 5. wl = 5 t0 t1 t2 t3 t4 t 5 t6 t 7 t8 t9 t n don t care transitioning data bank, col n nop write pre nop nop nop nop nop nop nop nop ck ck# command 1 dq 4 dqs, dqs # add ress 3 t wpst t wpre indicates a break in time scale di n + 3 di n + 2 di n + 1 di n t wr 2 valid dq input timing f igure 86 - d ata i nput t iming t dh t ds dm dq di b dq s, dqs# don t care transitioning data t dqsh t dqsl t wpre t wpst memory controller after the last data is written to the sdram during the write postamble, t wpst. data setup and hold times are shown in figure 86. all setup and hold times are measured from the crossing points of dqsx and dqsx\. these setup and hold values pertain to data input and data mask input. additionally, the half period of the data input strobe is speci ed by t dqsh and t dqsl. figure 76 shows the strobe to clock timing during a write. dqsx, dqsx\ must transition within 0.25 t ck of the clock transitions as limited by t dqss. all data and data mask setup and hold timings are measured relative to the dqsx, dqsx\ crossings, not the clock crossing. the write preamble and postamble are also shown. one clock prior to data input to the sdram, dqsx must be high and dqsx\ must be low. then for a half clock, dqsx is driven low (dqsx\ is driven high) during the write preamble. t wpre, likewise, dqsx must be kept low by the
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 131 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product precharge input a10 determines whether one bank or all banks are to be precharg ed and in the case where only one bank is to be precharged , inputs ba[2:0] select the array bank. when all banks are to be precharged, inputs ba[2:0] are treated as ?don?t care?. after a bank is precharged, it is in the idle state and must be activated prior to any read or write commands being issued. self refresh the self refresh command is initiated like a refresh command except cke is low. the dll is automatically disabled upon enterin g self refresh and is automatically enabled and reset upon exiting self refresh. all power supply inputs (including v refca and v refdq ) must be maintained at valid levels upon entry/exit and during self refresh mode operation. v refdq may oat or not drive vccq/2 while in the self refresh mode under certain conditions: vss logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 132 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 87 - s elf r efresh e ntry /e xit t iming notes: 1. the clock must be valid and stable meeting t ck specifications at least t cksre after entering self refresh mode, and at least t cksrx prior to exiting self refresh mode, if the clock is stopped or altered between states ta0 and tb0. if the clock remains valid and unchanged from entry and during self refresh mode, then t cksre and t cksrx do not apply; however, t ckesr must be satisfied prior to exiting at srx. 2. odt must be disabled and r tt off prior to entering self re fresh at state t1. if both r tt _ nom and r tt _ wr are disabled in the mode registers, odt can be a dont care. 3. self refresh entry (sre) is synchronous via a refresh command with cke low. 4. a nop or des command is required at t2 after the sre command is issued prior to the inputs becoming dont care. 5. nop or des commands are required prior to exiting self refresh mode until state te0. 6. t xs is required before any commands not requiring a locked dll. 7. t xsdll is required before any commands requiring a locked dll. 8. the device must be in the all banks idle state prior to entering self refresh mode. for exam- ple, all banks must be precharged, t rp must be met, and no data bursts can be in progress. 9. self refresh exit is asynchronous; however, t xs and t xsdll timings start at the first rising clock edge where cke high satisfies t isxr at tc1. t cksrx timing is also measured so that t isxr is satisfied at tc1. ck ck # command nop nop 4 sre(ref) 3 add ress ck e odt 2 reset# 2 vali d vali d 6 srx (nop) nop 5 t rp 8 t xs 6 , 9 t xs dll 7, 9 odtl t is t cpded t is t is enter self refresh mode (synchronous) exit self refresh mode (asynchronous) t0 t1 t2 tc 0 tc1 td0 tb 0 don t care te0 vali d vali d 7 vali d vali d vali d t ih ta0 tf0 indicates a break in time scale t cksrx 1 t cksre 1 t ckesr (min) 1
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 133 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product self refresh temperature (srt) extended temperature usage logic devices, inc imod ddr3 sdram module supports the optional extended temperature range up to 95 ? c while supporting self refresh/auto refresh and support tc temperatures >95 ? c 125 ? c with manual refresh only. when using self refresh/auto refresh and the case tem- perature is >85 ? c, srt and asr options must be used. the extended range temperature range sdram must be refreshed externally at 2x anytime the case temperature is >85 ? c. the external refreshing requirement is accomplished by reducing the refresh period from 64ms to 32ms. self refresh mode requires the use of asr or srt to support the extended temperature. field mr2 bits description srt asr t able 68: self refresh t emperature and auto self refresh d escription if asr is disabled (mr2[6]=0), srt must be programmed to indicate t oper during self refresh; * mr2[7] = 0: normal operating temperature range (0 ? c to 85 ? c) * mr2[7] = 1: extended operating temperature range (>85 ? c to 105 ? c) if asr is enabled (mr2[7]=1), srt must be set to 0, even if the extended temperature range is supported. *mr2[7]=0: srt is disabled. when asr is enabled, the sdram automatically provides self refresh power management functions, (refresh rate for all supported operating temperature values) *mr2[6]=1: asr is enabled (m7 must = 0) when asr is not enabled, the srt bit must be programmed to indicate t oper during self refresh operation. *mr2[6]=0: asr is disabled, must use manual self refresh (srt) 7 6 auto self refresh (asr) self refresh operation 0 0 1 1 t able 69: self refresh m ode s ummary self refresh mode is supported in the normal temperature range. self refresh mode is supported in normal and extended ( 95 ? c max) temperature ranges; when srt is enabled, it increases self refresh power consumption. self refresh mode is supported in normal and extended temperature ranges; self refresh power consumption may be temperature-dependent. illegal. 0 1 0 1 permitted operating temperature range for self refresh mode mr2[7] (srt) mr2[6] (asr) normal (0c to 85c) normal and extended (0c to 95c) normal and extended (0c to 95c) power-down mode power-down is synchronously entered when cke is registered low coincident with a nop or des command. cke is not allowed to go low while either an mrs, mpr, zqcal, read or write operation is in progress. cke is allowed to go low while any of the other legal operations are in progress. however, the power-down icc speci cations are not applicable until such operations have been completed. depending on the previous sdram state and the command issued prior to cke going low, certain timing constraints must be satis ed (as noted in table 70). timing diagrams detailing the different power-down mode entry and exits are shown in figure 88 through figure 97.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 134 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product idle or active idle or active active active active active active idle power-down idle t able 70: command to power-down e ntry p arameters t actpden t prpden t rdpden t wrpden t wrapden t refpden t xpdll t mrspden activate precharge read or readap write: bl8otf, bl8mrs, bc4otf write: bc4mrs writeap: bl8otf, bl8mrs, bc4otf writeap: bc4mrs refresh refresh mode register set last command prior to cke low 1 1 t ck 1 t ck rl = 4 t ck + 1 t ck wl + 4 t ck + t wr/ t ck wl + 2 t ck + t wr/ t ck wl + 4 t ck + wr + 1 t ck wl + 2 t ck + wr + 1 t ck 1 t ck greater of 10 t ck or 24ns t mod figure 95 figure 96 figure 91 figure 92 figure 92 figure 93 figure 93 figure 94 figure 98 figure 97 sdram status parameter (min) parameter value figure entering power-down mode disables the input and output buffers, excluding ck, ck\, odt, cke and reset\. nop or des commands ar e required until t cpded has been satis ed, at which time all speci ed input/output buffers will be disabled. the dll should be in a locked state when power-down is entered for the fastest mode timing. if the dll is not locked during the power-down entry, the dll must be reset after exiting power-down for proper read operation as well as synchronous odt operation. during power-down entry, if any bank remains open after all in-progress commands are complete, the sdram will be in active powe r-down. if all banks are closed after all in-progress commands are complete, the sdram will be in precharge power-down mode or fast exit mode. when entering precharge power-down, the dll is turned off in slow exit mode or kept on in fast exit mode. the dll remains on when entering active power-down as well. odt has special timing constraints when slow exit mode, precharge power- down is enabled and entered. refer to ?asynchronous odt mode? for detailed odt usage requirements in slow exit mode precharge power-down. a summary of the two power-down modes is listed in table 71. while in either power-down state, cke is held low, reset\ is held high, and a stable clock signal must be maintained. odt must be in a valid state but all other input signals are a ?don?t care?. if reset\ goes low during power-down, the sdram will switch out of power-down and go into the reset state. after cke is registered low, cke must remain low until t pd (min) has been satis ed. the maximum time allowed for power-down duration is t pd (max) (9 x trefi). the power-down states are synchronously exited when cke is registered high (with a required nop or des command). cke must be m aintained high until t cke has been satis ed. a valid, executable command may be applied after power-down exit latency, t xp, t xpdll have been satis ed. a sum- mary of the power-down modes is listed in table 71. d l l s t a t e active (any bank open) precharge (all banks precharged) t able 71: power-down m odes on on off relevant parameters mr1[12] t xp to any other valid command t xp to any other valid command t xdll to commands that require the dll to be locked (read, rdap, odt on). t xp to any other valid command. sdram state ?don?t care? 1 0 fast fast slow power-down exit
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 135 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 88 - a ctive p ower -d own e ntry and e xit ck ck# command nop nop nop nop address cke t ck t ch t cl enter power-down mode exit power-down mode dont care valid valid valid t cpded valid t is t ih t ih t is t0 t1 t2 ta0 ta1 ta2 ta3 ta4 nop t xp t cke (min) indicates a break in time scale t pd f igure 89 - p recharge p ower -d own (f ast -e xit m ode ) e ntry and e xit tckemin tckemin ck ck# p o n p o n p o n p o n d n a m m o c cke t ck t ch t cl enter power-down mode exit power-down mode t pd valid t cpded t is t ih t is t0 t1 t2 t3 t4 t5 ta0 ta1 nop dont care indicates a break in time scale t cke (min) t xp
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 136 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 90 - p recharge p ower -d own (s low -e xit m ode ) e ntry and e xit notes: 1. any valid command not requiring a locked dll. 2. any valid command requiring a locked dll. ck ck# command p o n p o n p o n cke t ck t ch t cl enter power-down mode exit power-down mode t pd valid 2 valid 1 pre t xpdll t cpded t is t ih t is t0 t1 t2 t3 t4 ta ta1 tb nop dont care indicates a break in time scale t xp t cke (min) f igure 91 - p ower -d own e ntry a fter read or read with a uto p recharge (rdap) t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta6 ta7 ta8 ta9 don t care transitionin g data ta10 ta11 ta12 nop vali d read/ rdap nop nop nop nop nop nop nop nop nop ck ck # command dq bl8 dq bc4 dqs, dqs# add ress ck e t cpded t is t pd power- down or self refresh entry indicates a break in time scale t rdpden di n + 3 di n + 1 di n + 2 di n rl = al + cl di n + 3 di n + 2 di n + 1 di n di n + 6 di n + 7 di n+ 5 di n + 4
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 137 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 92 - p ower -d own e ntry a fter write notes: 1. cke can go low 2 t ck earlier if bc4mrs. t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta6 ta7 tb 0 tb 1 tb 2 tb 3 tb 4 nop write valid nop nop nop nop nop nop nop nop nop nop nop ck ck # command dq bl8 dq bc4 dqs, dqs# add ress ck e t cpded power- down or self refresh entry 1 don t car e transitioning data t wrpden di n + 3 di n + 1 di n + 2 di n t pd indicates a break in time scale di n + 3 di n + 2 di n + 1 di n di n + 6 di n + 7 di n + 5 di n+ 4 t is wl = al + cwl t wr f igure 93 - p ower -d own e ntry a fter write with a uto p recharge (wrap) notes: 1. t wr is programmed through mr0[11:9] and represents t wr (min)ns/ t ck rounded up to the next integer t ck. 2. cke can go low 2 t ck earlier if bc4mrs. t0 t1 ta0 ta1 ta2 ta3 ta4 ta5 ta 6 ta7 tb 0 tb 1 don t car e transitioning data tb 2 tb 3 tb 4 nop wrap vali d nop nop nop ck ck# command dq bl8 dq bc4 dqs, dqs# add ress a10 cke t pd t wrapden power- down or self refresh entry 2 start internal pre char ge t cpded t is indicates a break in time scale di n + 3 di n + 2 di n + 1 di n di n + 6 di n + 7 di n + 5 di n + 4 di n + 3 di n + 2 di n + 1 di n wr 1 wl = al + cwl nop nop nop nop nop nop nop nop
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 138 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 94 - refresh to p ower -d own e ntry notes: 1. after cke goes high during t rfc, cke must remain high until t rfc is satisfied. ck ck# command refresh nop nop nop nop valid cke t ck t ch t cl t cpded t refpden t is t0 t1 t2 t3 ta0 ta1 ta2 tb0 t xp (min) t rfc (min) 1 dont care indicates a break in time scale t cke (min) t pd f igure 95 - activate to p ower -d own e ntry tcke ck ck# c ommand address active nop nop cke t ck t ch t cl dont care t cpded t actpden valid t is t0 t1 t2 t3 t4 t5 t6 t7 t pd
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 139 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 96 - precharge to p ower -d own e ntry ck ck# command address cke t ck t ch t cl dont care t cpded t prepden t is t0 t1 t2 t3 t4 t5 t6 t7 t pd all/single bank pre nop nop f igure 97 - mrs c ommand to p ower -d own e ntry ck ck# cke t ck t ch t cl t cpded address t is t0 t1 t2 ta0 ta1 ta2 ta3 ta4 t pd dont care indicates a break in time scale valid command mrs nop nop nop nop nop t mrspden
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 140 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 98 - p ower -d own e xit to r efresh to p ower -d own e ntry notes: 1. t xp must be satisfied before issuing the command. 2. t xpdll must be satisfied (referenced to the registration of power-down exit) before the next power-down can be entered. ck ck# cke t ck t ch t cl enter power-down mode enter power-down mode exit power-down mode t pd t cpded t is t ih t is t0 t1 t2 t3 t4 ta0 ta1 tb0 dont care indicates a break in time scale command nop nop nop nop refresh nop nop t xp 1 t xpdll 2 reset the reset signal (reset\) is an asynchronous signal that triggers any time it drops low and there are no restrictions about whe n it can go low. after reset\ is driven low, it must remain low for 100ns. during this time, the outputs are disabled, odt (r tt ) turns off (high-z) and the ddr3 sdram resets itself. cke should be brought low prior to reset\ being driven high. after reset\ goes high, the sdram must be re-initialized as though a normal power up were executed (see figure 99). all refresh counters on the sdram are reset and data stored in the sdram is assumed un known after reset\ has been driven low.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 141 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 99 - reset s equence cke r tt ba[2:0] all voltage supplies valid and stable high-z dm dqs high-z add ress a10 ck ck# t cl command nop t0 ta0 don t care t cl t is odt dq high-z tb 0 t dllk mr1 with dll enable mrs mrs ba0 = h ba1 = l ba2 = l ba0 = l ba1 = l ba2 = l code code code code vali d vali d vali d vali d normal operation mr2 mr3 mrs mrs ba0 = l ba1 = h ba2 = l ba0 = h ba1 = h ba2 = l code code code code tc0 td0 reset# sta ble an d vali d clo ck vali d vali d dram rea dy for external commands t1 t zq init a10 = h zq cl t is t ioz vali d vali d vali d system reset (warm boot) zq cal mr0 with dll reset t=10ns (min) t = 100ns (min) indicates a break in time scale t = 500s (min) t xpr t mrd t mrd t mrd t mod t (min) = max (10ns, 5 t ck) t ck
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 142 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product on-die termination (odt) odt is a feature that enables the sdram to enable/disable on-die termina- tion resistance for each dq, ldqsx, ldqsx\ , udqsx, udqsx\ ldmx and udmx for the four words contained in ldi?s ddr3 imod. the odt feature is designed to improve signal integrity of the memory array/ sub-system by enabling the ddr3 memory controller to independently turn on or off the sdrams internal termination resistance for any grouping of sdram devices. the odt feature is not supported during dll disable mode. a simple functional representation of the sdram odt feature is shown in figure 100. the switch is enabled by the internal odt control logic, which uses the external odt ball and other control information. functional representation of odt the value of r tt (odt termination value) is determined by the settings of several mode register bits (see table 75). the odt ball is ignored while in self refresh mode (must be turned off prior to self refresh entry) or if mode registers mr1 and mr2 are programmed to disable odt. odt is comprised of nominal odt and dynamic odt modes and either of these can function in synchronous or asynchronous modes (when the dll is off during precharge power-down or when the dll is synchroniz- ing). nominal odt is the base termination and is used in any allowable odt state. dynamic odt is applied only during writes and provides otf switching from no r tt or r tt _nom to r tt _wr. the actual effective termination, r tt _eff may be different from the r tt targeted due to nonlinearity of the termination. for r tt _eff values and calculations, see ?odt characteristics?. odt v cc q/2 r tt switch dq, dqs, dqs#, to other circuitry such as rcv, . . . dm f igure 100 - o n -d ie t ermination nominal odt odt (nom) is the base termination resistance for each applicable ball, enabled or disabled via mr1[9,6,2] (see figure 46), and it is turned on or off via the odt ball. t able 72: power-down m odes mr1[9,6,2] odt pin sdram termination state sdram state n o t e s r tt _nom disabled, odt off r tt _nom disabled, odt on r tt _nom enabled, odt off r tt _nom enabled, odt on r tt _nom reserved, odt on or off any valid any valid except self refresh, read any valid any valid except self refresh, read illegal 1,2 1,3 1,2 1,3 000 000 000-101 000-101 110 and 111 0 1 0 1 x odt must be disabled during reads. the 3. r tt _nom value is restricted during writes. dynamic odt is applicable if enabled. notes: assumes dynamic odt is disabled. 1. odt is enabled and active during most writes for proper termination, 2. but it is not illegal to have it off during writes.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 143 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product nominal odt resistance r tt _nom is de ned by mr1[9,6,2], as shown in figure 46. the r tt _nom termination value applies to the output pins previously mentioned. ddr3 sdram imods support multiple r tt _nom values based on rzq/n where n can be 2,4,6,8 or 12 and rzq is 240 1%. r tt _nom termina- tion is allowed any time after the sdram is initialized, calibrated and not performing read accesses or when it is not in self refresh mode. write access uses r tt _nom id dynamic odt (r tt _wr) is disabled. if r tt _nom is used during writes, only rzq/2, rzq/4 and rzq/6 are allowed (see table 71). odt timings are summarized in table 73, as well as, listed in table 50. examples of nominal odt timing are shown in conjunction with the synchronous mode of operation in ?synchronous odt mode?. t able 73: odt p arameter symbol description begins at de ned to units odt registered high odt registered high odt registered high odt registered high odt registered high or write registration with odt high write registration with odt high completion of odtl on completion of odtl off odtl on odtl off t aonpd t aoffpd odth4 odth8 t aon t aof odt synchronous turn on delay odt synchronous turn off delay odt asynchronous on delay odt asynchronous on delay odt minimum high time after odt assertion or write (bc4) odt minimum high time after write (bl8) odt turn-on relative to odtl on completion odt turn-off relative to odtl off completion r tt _on t aon r tt _on t aof r tt _on r tt _off odt registered low odt registered low r tt _on r tt _off cwl + al - 2 cwl + al - 2 1-9 1-9 4 t ck 6 t ck see table 50 0.5 t ck 0.2 t ck t ck t ck ns ns t ck t ck ps t ck de nition for all ddr3 bins dynamic odt in certain applications, to further enhance signal integrity on the data bus, it is desirable that the termination strength, be changed without issuing an mrs command, essentially changing the odt termination resistance on-the- y. with dynamic odt (r tt _wr) enabled, the sdram switches from nominal odt (r tt _nom) to dynamic odt when beginning a write burst and subsequently switches back to nominal odt at the completion of the write burst sequence. this requirement and the supporting dynamic odt feature of the ddr3 sdram makes it feasible and is described in further detail below: dynamic odt f unctional d escription : the dynamic odt mode is enabled if either mr2[9] or mr2[10] is set to ?1?. dynamic odt is not supported during dll disable mod e, so r tt _wr must be disabled. the dynamic odt function is described, as follows: two r ? tt values are available ? r tt _nom and r tt _wr: the value of r ? tt _nom is preselected via mr1[9,6,2] the value for r ? tt _wr is preselected via mr2[10,9] during sdram operations without read or write commands, the termination is controlled as follows: ? termination on/off timing is controlled via the odt ball and latencies odtl on and odtl off ? nominal termination strength r ? tt _nom is used when a write command (wr, wrap, wrs4, wrs8, wraps4, wraps8) is registered and if dynamic odt is enabled, the odt ter- ? mination is controlled as follows: a latency of odtlcnw after the write command: termination strength r ? tt _nom switches to r tt _wr a latency of odtlcwn8 (for bl8, xed or otf) or odtlcwn4 (for bc4, xed or otf) after the write command: termination ? strength r tt _wr switches back to r tt _nom on/off termination timing is controlled via the odt ball and determined by odtl on, odtl off, odth4 and odth8. ? during the ? t adc transition window, the value of r tt is unde ned odt is constrained during writes and when dynamic odt is enabled (see table 74). nominal odt
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 144 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 74: dynamic odt s pecific p arameters symbol description begins at de ned to units write registration write registration write registration odtl cnw odtl cnw odtl cwn4 odtl cwn8 t adc change from r tt _nom to r tt _wr change from r tt _wr to r tt _nom (bc4) change from r tt _wr to r tt _nom (bl8) r tt change skew r tt switched from r tt _nom to r tt _wr r tt switched from r tt _wr to r tt _nom r tt switched from r tt _wr to r tt _nom r tt trans complete wl - 2 4 t ck + odtl off 6 t ck + odtl off 0.5 t ck 0.2 t ck t ck t ck t ck t ck de nition for all ddr3 bins t able 75: mode registers for rtt_nom m9 m6 m2 rtt_nom (rzq) rtt_nom(ohms) rtt_nom mode restriction 0 0 0 0 1 1 1 1 off rzq/4 rzq/2 rzq/6 rzq/12 rzq/8 reserved reserved n/a self refresh self refresh, write n/a n/a 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 off 60 120 40 20 30 reserved reserved mr1(rtt_nom) t able 76: mode registers for r tt _wr m10 m2 r tt _nom (rzq) r tt _nom(ohms) 0 0 1 1 n/a n/a n/a n/a rzq/4 rzq/2 reserved n/a n/a n/a n/a 0 1 0 1 n/a n/a n/a n/a 60 120 reserved n/a n/a n/a n/a mr1(r tt _nom) dynamic odt off: write does not affect r tt _nom t able 77: timing diagrams for dynamic odt figure title figure 101 figure 102 figure 103 figure 104 figure 105 dynamic odt: odt asserted before and after the write, bc4 dynamic odt: without write command dynamic odt: odt pin asserted together with write command for 6 ck cycles, bl8 dynamic odt: odt pin asserted with write command for 6 ck cycles, bc4 dynamic odt: odt pin asserted with write command for 4 ck cycles, bc4
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 145 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 101 - d ynamic odt: odt a sserted b efore and a fter the write, bc4 notes: 1. via mrs or otf. al = 0, cwl = 5. r tt _ nom and r tt _ wr are enabled. 2. odth4 applies to first registering odt high and then to the registration of the write command. in this example, odth4 is satisfied if odt goes low at t8 (four clocks after the write command). t0 t1 t2 t3 t4 t5 t 6t7t8t9 odtl on odtl cw n 4 odtl cn w wl odtl off t10 t11 t12 t13 t14 t15 t17 t16 ck ck # command add ress r tt odt dq dqs, dqs# vali d wrs4 p o n p o n p o n p o n p o n nop nop don t care transitioning r tt _ wr r tt _ nom r tt _ nom di n + 3 di n + 2 di n + 1 di n nop nop nop nop nop nop nop nop nop nop odth4 odth4 t aon (min) t adc (min) t adc (min) t aof (min) t aon (max) t adc (max) t adc (max) t aof (max) f igure 102 - d ynamic odt: w ithout write c ommand notes: 1. al = 0, cwl = 5. r tt _ nom is enabled and r tt _ wr is either enabled or disabled. 2. odth4 is defined from odt registered high to odt registered low; in this example, odth4 is satisfied. odt registered low at t5 is also legal. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 odtl off t10 t11 ck ck# r tt don t care transitionin g command vali d vali d vali d vali d vali d vali d vali d vali d vali d vali d vali d vali d add ress dqs, dqs# dq odth4 odtl on t aon (max) t aon (min) t aof (min) t aof (max) odt r tt _ nom
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 146 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 103 - d ynamic odt: odt p in a sserted t ogether with write c ommand for 6 c lock c ycles , bl8 notes: 1. via mrs or otf; al = 0, cwl = 5. if r tt _ nom can be either enabled or disabled, odt can be high. r tt _ wr is enabled. 2. in this example, odth8 = 6 is satisfied exactly. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 odtl cw n 8 odtl on odtl cn w wl t aof (max) t10 t11 ck ck# add ress r tt odt dq dqs, dqs# di b + 3 di b + 2 di b + 1 di b di b+ 7 di b + 6 di b + 5 di b + 4 vali d don t care transitioning command wrs8 nop nop nop nop nop nop nop nop nop nop nop r tt _ wr odth8 odtl off t adc (max) t aon (min) t aof (min) f igure 104 - d ynamic odt: odt p in a sserted with write c ommand for 6 c lock c ycles , bc4 notes: 1. via mrs or otf. al = 0, cwl = 5. r tt _ nom and r tt _ wr are enabled. 2. odth4 is defined from odt registered high to odt registered low, so in this example, odth4 is satisfied. odt registered low at t5 is also legal. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 odtl on odtl cn w wl t10 t11 ck ck# odtl cw n 4 dqs, dqs# address vali d don t care transitioning odtl off command wrs4 nop nop nop nop nop nop nop nop dq di n+ 3 di n + 2 di n + 1 di n t adc (min) t aof (min) t aof (max) t adc (max) t adc (max) t aon (min) odth4 odt r tt r tt _ wr r tt _ nom nop nop nop
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 147 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 105 - d ynamic odt: odt p in a sserted with write c ommand for 4 c lock c ycles , bc4 notes: 1. via mrs or otf. al = 0, cwl = 5. r tt _ nom can be either enabled or disabled. if disabled, odt can remain high. r tt _ wr is enabled. 2. in this example odth4 = 4 is satisfied exactly. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 odtl on odtl cn w wl t10 t11 ck ck# odtl cw n 4 dqs, dqs# add ress valid r tt _ wr command wrs4 nop nop nop nop nop nop nop nop nop don t care transitioning dq di n di n + 3 di n + 2 di n + 1 odth4 t adc (max) t aon (min) t aof (min) t aof (max) odtl off r tt r tt _ wr odt nop nop synchronous odt mode synchronous odt is selected whenever the dll is turned on and locked while r tt _nom or r tt _wr is enabled. based on the power-down de nition, these modes are: any bank active with cke high ? refresh mode with cke high ? dle mode with cke high ? active power-down mode (regardless of ? mr0[12]) precharge power-down mode if dll is ? enabled during precharge power-down by mr0[12] odt latency and posted odt in synchronous odt mode, r tt turns on odtl on clock cycles after odt is sampled high by a rising clock edge and turns off odtl off clock cycles after odt is registered low by a rising clock edge. the actual on/off times varies by t aon and t aof around each clock edge (see table 78). the odt latency is tied to the write latency (wl) by odtl on =wl-2 and odtl off = wl- 2. since write latency is made up of cas write latency (cwl) and additive latency (al), the al value programmed into the mode regis- ter mr1[4,3], also applies to the odt signal. the sdram?s internal odt signal is delayed a number of clock cycles de ned by the al relative to the external odt signal. thus, odtl on = cwl + al ? 2 and odtl off = cwl + al ? 2.
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 148 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product synchronous odt t iming p arameters synchronous odt mode uses the following timing parameters: odtl on, odtl off, odth4, odth8, t aon and t aof (see table 78 and figure 106). the minimum r tt turn-on time ( t aon [min]) is the point at which the device leaves high-a and odt resistance begins to turn on. maximum r tt turn-on time ( t aon [max]) is the point at which odt resistance is fully on. both are measured relative to odtl on. the minimum r tt turn-off time ( t aof [min]) is the point at which the device starts to turn-off odt resistance. maximum r tt turn-off time ( t aof [max]) is the point at which odt has reached high-z. both are measured from odtl off. when odt is asserted, it must remain high until odth4 is satis ed. if a write command is registered by the sdram with odt high, then odt must remain high until odth4 (bc4) or odth8 (bl8) after the write command (see figure 107). odth4 and odth8 are measured from odt r egistered high to odt registered low or from the registration of a write command until odt is registered low. t able 78: synchronous odt p arameters symbol description begins at de ned to units odt registered high odt registered high odt registered high, or write registration with odt high write registration with odt high completion of odtl on completion of odtl off odtl on odtl off odth4 odth8 t aon t aof odt synchronous turn-on delay odt synchronous turn-off delay odt minimum high time after odt assertion or write (bc4) odt minimum high time after write (bl8) odt turn-on relative to odtl on completion odt turn-off relative to odtl off completion r tt _on t aon r tt _off t aof odt registered low odt registered low r tt _on r tt _off cwl + al - 2 cwl + al - 2 4 t ck 6 t ck see table 50 0.5 t ck 0.2 t ck t ck t ck t ck t ck ps t ck de nition for all ddr3 bins f igure 106 - s ynchronous odt notes: 1. al = 3; cwl = 5; odtl on = wl = 6.0; odtl off = wl - 2 = 6. r tt _ nom is enabled. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 cwl - al = 3 al = 3 t aon (max) t10 t11 t12 ck ck # r tt odt r tt _ nom ck e odtl off = cwl + al - 2 odtl on = cwl + al - 2 odth4 (min) t aon (min)
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 149 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 107 - s ynchronous odt (bc4) notes: 1. wl = 7. r tt _ nom is enabled. r tt _ wr is disabled. 2. odt must be held high for at least odth4 after assertion (t1). 3. odt must be kept high odth4 (bc4) or odth8 (bl8) after the write command (t7). 4. odth is measured from odt first registered high to odt first registered low or from the registration of the write command with odt high to odt registered low. 5. although odth4 is satisfied from odt registered high at t6, odt must not go low before t11 as odth4 must also be satisfied from the registration of the write command at t7. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t aof (max) t aof (min) t aon (max) t aof (max) t10 t11 t12 t13 t14 t15 t17 t16 ck ck# r tt ck e nop wrs4 nop nop nop nop nop nop command don t care transitioning t aon (min) r tt _ nom odtloff = wl - 2 odth4 (min) odth4 odtl off = wl - 2 odtl on = wl - 2 t aon (min) t aon (max) odth4 odtl on = wl - 2 t aof (min) odt r tt _ nom nop nop nop nop nop nop nop nop nop nop odt off d uring reads as the ddr3 sdram cannot terminate and drive at the same time, r tt must be disabled at least one-half clock cycle before the read preamble by driving the odt ball low. r tt may not be enabled until the end of the postamble as shown in figure 108. f igure 108 - odt d uring read s notes: 1. odt must be disabled externally during reads by driving odt low. for example, cl = 6; al = cl - 1 = 5; rl = al + cl = 11; cwl = 5; odtl on = cwl + al - 2 = 8; odtl off = cwl + al - 2 = 8. r tt _ nom is enabled. r tt _ wr is a dont care. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t17 t16 ck ck# vali d add ress di b + 3 di b + 2 di b + 1 di b di b + 7 di b + 6 di b+ 5 di b+ 4 dq dqs, dqs# don t care transitioning command nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop read odtl on = cwl + al - 2 odt t aon (max) rl = al + cl odtl off = cwl + al - 2 t aof (min) r tt r tt _ nom r tt _ nom t aof (max)
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 150 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product asynchronous odt mode asynchronous odt mode is available when the sdram runs in dll on mode and when either r tt _nom or r tt _wr is enabled; however, the dll is tem- porarily turned off in precharged power-down standby via mr0[12]. additionally, odt operates asynchronously when the dll is sy nchronizing after being reset. see ?power-down mode? for de nition and guidance over power-down details. in asynchronous odt timing mode, the internal odt command is not delayed by al relative to the external odt command. in asynch ronous odt mode, odt controls r tt by analog time. the timing parameters t aonpd and t aofpd (see table 79) replace odtl on/ t aon and odtl off/ t aof respectively, when odt operates asynchronously (see figure 109). the minimum r tt turn-on time ( t aonpd [min]) is the point at which the device termination circuit leaves high-z and odt resistance begins to turn-on. maxi- mum r tt turn-on time ( t aonpd [max]) is the point at which odt resistance is fully on. t aonpd (min) and t aonpd (max) are measured from odt being sampled high. the minimum r tt turn-off time ( t aofpd [min]) is the point at which the device termination circuit starts to turn off odt resistance. maximum r tt turn-off time ( t aofpd [max]) is the point at which odt has reached high-z. t aofpd (min) and t aofpd (max) are measured from odt being sampled low. t able 79: asynchronous odt t iming p arameters for a ll s peed b ins symbol description min max units t aon pd t aof pd asynchronous r tt turn-on delay (power-down with dll off) asynchronous r tt turn-off delay (power-down with dll off) 2 2 8.5 8.5 ns ns f igure 109 - a synchronous odt t iming with f ast odt t ransition notes: 1. al is ignored. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t aonpd (max) t aofpd (max) t10 t11 t12 t13 t14 t15 t17 t16 ck ck # r tt odt r tt _ nom don t care transitioning ck e t ih t is t ih t is t aofpd (min) t aonpd (min)
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 151 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product t able 80: odt p arameters for power-down (dll off) e ntry and e xit t ransition p eriod description min max power-down entry transition period (power-down entry) power-down entry transition (power-down exit) odt to r tt turn-on delay (odtl on = wl - 2) odt to r tt turn-off delay (odtl off = wl - 2) t an pd greater of: t an pd or t rfc - refresh to cke low t an pd + t xpdll wl - 1 (greater of odtl off + 1 or odtl on + 1) lesser of: t an pd (min) [1ns] or odl on x t ck + t aon (min) lesser of: t aof pd (min) [1ns] or odl off x t ck + t aof (min) lesser of: t an pd (min) [1ns] or odl on x t ck + t aon (min) lesser of: t aof pd (min) [1ns] or odl off x t ck + t aof (min) synchronous to asynchronous odt mode transition (power-down entry) there is a transition period around power-down entry (pde) where the sdram?s odt may exhibit either synchronous or asynchronous behavior. this transition period occurs if the dll is selected to be off when in precharge power-down mode by the setting of mr0[12] = 0. powe r-down entry begins t anpd prior to cke rst being registered low and it ends when cle is rst registered low. t anpd is equal to the greater of odtl off + 1 t ck or odtl on + 1 t ck. if a refresh command has been issued, and it is in progress when cke goes low, power-down entry will end t rfc after the refresh command rather than when cke is rst registered low. power-down entry will then become the greater of t anpd and t rfc ? refresh command to cke registered low. odt assertion during power-down entry results in an r tt change as early as the lesser of t aonpd (min) and odtl on x t ck + t aon (min) or as late as the greater of t aonpd (max) and odtl on x t ck + t aon (max). odt de-assertion during power-down entry may result in an r tt change as early as the lesser of t aofpd (min) and odtl off x t ck + t aof (min) or as late as the greater of t aofpd (max) and odtl off x t ck + t aof (max). table 80 summarizes these parameters. if the al has a large value, the uncertainty of the state of r tt becomes quite large. this is because odtl on and odtl off are derived from the wl and wl is equal to cwl + al. figure 110 shows three different cases; odt_a: synchronous behavior before ? t anpd odt_b: odt state changes during the transition period with ? t aonpd (min) less than odtl on x t ck + t aon (min) and t aonpd (max) greater than odtl on x t ck + t aon (max) odt_c: odt state changes after the transition period with asynchronous behavior ?
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 152 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product asynchronous to synchronous odt mode transition (power-down exit) the sdram?s odt may exhibit either asynchronous or synchronous behavior during power-down exit (pdx). this transition period o ccurs if the dll is selected to be off when in precharge power-down mode by setting mr0[12] to ?0?. power-down exit begins t anpd prior to cke rst being regis- tered high and it ends t xpdll after cke is rst registered high. t anpd is equal to the greater of odtl off + 1 t ck or odtl on + 1 t ck. the transition period is t anpd plus t xpdll. odt assertion during power-down exit results in an r tt change as early as the lesser of t aonpd (min) and odtl on x t ck + t aon (min) or as late as the greater of t aonpd (max) and odtl on x t ck + t aon (max). odt de-assertion during power-down exit may result in an r tt change as early as the lesser of t aofpd (min) and oftl off x t ck + t aof (min) or as late as the greater of t aofpd (max) and odtl off x t ck + t aof (max). table 80 summarizes these parameters. if the al has a large value, the uncertainty of the r tt state becomes quite large. this is because odtl on and odtl off are derived from the wl, and the wl is equal to cwl + al. figure 111 shows three different cases. odt c: asynchronous behavior before ? t anpd odt b: odt state changes during the transition period with ? t aofpd (min) less than odtl off x t ck + t aof (min) and odtl off x t ck + t aof (max) greater than t aofpd (max) odt a: odt state changes after the transition period with synchronous response ? f igure 110 - s ynchronous to a synchronous t ransition d uring p recharge p ower -d own (dll o ff ) e ntry notes: 1. al = 0; cwl = 5; odtl off = wl - 2 = 3. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t aofpd (max) odtl off t10 t11 t12 t13 ta0 ta1 ta3 ta2 ck ck# dram r tt b asynchronous or synchronous r tt _ nom dram r tt c asynchronous r tt _ nom don t care transitioning ck e nop nop nop nop nop command nop ref nop nop nop nop nop nop nop nop nop nop nop pde transition perio d indicates a break in time scale odtl off + t aofpd (min) t aofpd (max) t aofpd (min) odtl off + t aofpd (max) t aofpd (min) t anpd t aof (min) t aof (max) dram r tt a synchronous r tt _ nom odt a synchronous odt c asynchronous odt b asynchronous or synchronous t rfc (min)
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 153 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product f igure 111 - a synchronous to s ynchronous t ransition d uring p recharge p ower -d own (dll o ff ) e xit notes: 1. cl = 6; al = cl - 1; cwl = 5; odtl off = wl - 2 = 8. t0 t1 t2 ta0 ta1 ta2 ta3 ta4 ta5 ta 6 t b0 tb1 tb2 tc0 tc1 td 0 td 1 tc2 ck ck# don t care transitioning odt c synchronous p o n p o n nop command nop nop nop nop r tt b asynchronous or synchronous dram r tt a asynchronous dram r tt c synchronous r tt _ nom nop nop odt b asynchronous or synchronous ck e t aof (min) r tt _ nom indicates a break in time scale odtl off + t aof (min) t aofpd (max) odtl off + t aof (max) t xpdll t aof (max) odtl off odt a asynchronous pdx transition period t aofpd (min) t aofpd (max) t anpd t aofpd (min) r tt _ nom nop nop nop nop nop
logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 154 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product asynchronous to synchronous odt mode transition (short cke pulse) if the time in the precharge power down or idle states is very short (short cke low pules), the power-down entry and power-down exit transition periods will overlap. when overlap occurs, the response of the sdram?s r tt to a change in the odt state may be synchronous or asynchronous from the start of the power-down entry transition period to the end of the power-down exit transition period even if the entry period ends later than the exit period. (see figure 112). if the time in the idle state is very short (short cke high pulse), the power-down exit and power-down entry transition periods overlap. when this overlap occurs, the response of the sdram?s r tt to a change in the odt state may be synchronous or asynchronous from the start of the power-down exit transition period to the end of the power-down entry transition period (see figure 113). f igure 112 - t ransition p eriod for s hort cke low c ycles with e ntry and e xit p eriod o verlapping notes: 1. al = 0, wl = 5, t anpd = 4. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 ta0 ta1 ta2 ta3 ta4 ck ck# ck e command don t care transitionin g t xpdll t rfc (min) nop nop nop nop nop nop nop nop nop nop ref p o n p o n nop nop pde transition period pdx transition perio d indicates a break in time scale t anpd short cke low transition period (r tt chan ge asynchronous or syn chronous) t anpd f igure 113 - t ransition p eriod for s hort cke high c ycles with e ntry and e xit p eriod o verlapping notes: 1. al = 0, wl = 5, t anpd = 4. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 ck ck# c ommand don t care transitionin g nop nop nop nop nop nop nop nop nop nop nop p o n p o n nop nop nop t anpd t xpdll indicates a break in time scale t a 0 t a 1 t a 2 t a 3 t a 4 cke short cke high transition period (r tt chan ge asynchronous or synchonous) t anpd
logic devices incorporated reserves the right to make corrections, modi cations, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant informa- tion before placing orders and should verify that such information is current and complete. logic devices does not assume any l iability arising out of the application or use of any product or circuit described herein. in no event shall any liability exceed the product purcha se price. products of logic devices are not warranted nor intended to be used for medical, life support, life saving, critical control or safety appl ications, unless pursu- ant to an express written agreement with logic devices. furthermore, logic devices does not authorize its products for use as c ritical compo- nents in life-support systems where a malfunction or failure may reasonably be expected to result in signi cant injury to the user. logic devices incorporated www.logicdevices.com jul 06, 2009 lds-L9D345G72BG5-a 155 4.5 gb, ddr3, 64 m x 72 integrated module (imod) advance information L9D345G72BG5 high performance, integrated memory module product r evision h istory revision engineer issue date description of change a 07.06..2009 initiate dh/jm

▲Up To Search▲

Price & Availability of L9D345G72BG5

	To Download L9D345G72BG5 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .